pexpert/arm/pe_omap3530.h

150 #define INTCPS_SYSCONFIG      (gOmapInterruptControllerBase + 0x0010)
151 #define INTCPS_SYSSTATUS      (gOmapInterruptControllerBase + 0x0014)
152 #define INTCPS_SIR_IRQ        (gOmapInterruptControllerBase + 0x0040)
153 #define INTCPS_SIR_IFQ        (gOmapInterruptControllerBase + 0x0044)
154 #define INTCPS_CONTROL        (gOmapInterruptControllerBase + 0x0048)
155 #define INTCPS_PROTECTION     (gOmapInterruptControllerBase + 0x004C)
156 #define INTCPS_IDLE           (gOmapInterruptControllerBase + 0x0050)
157 #define INTCPS_IRQ_PRIORITY   (gOmapInterruptControllerBase + 0x0060)
158 #define INTCPS_FIQ_PRIORITY   (gOmapInterruptControllerBase + 0x0064)
159 #define INTCPS_THRESHOLD      (gOmapInterruptControllerBase + 0x0068)
160 #define INTCPS_ITR(n)         (gOmapInterruptControllerBase + 0x0080 + (0x20 * (n)))
161 #define INTCPS_MIR(n)         (gOmapInterruptControllerBase + 0x0084 + (0x20 * (n)))
162 #define INTCPS_MIR_CLEAR(n)   (gOmapInterruptControllerBase + 0x0088 + (0x20 * (n)))
163 #define INTCPS_MIR_SET(n)     (gOmapInterruptControllerBase + 0x008C + (0x20 * (n)))
164 #define INTCPS_ISR_SET(n)     (gOmapInterruptControllerBase + 0x0090 + (0x20 * (n)))
165 #define INTCPS_ISR_CLEAR(n)   (gOmapInterruptControllerBase + 0x0094 + (0x20 * (n)))
166 #define INTCPS_PENDING_IRQ(n) (gOmapInterruptControllerBase + 0x0098 + (0x20 * (n)))
167 #define INTCPS_PENDING_FIQ(n) (gOmapInterruptControllerBase + 0x009C + (0x20 * (n)))
168 #define INTCPS_ILR(m)         (gOmapInterruptControllerBase + 0x0100 + (0x04 * (m)))