Lines Matching refs:gOmapInterruptControllerBase
60 #define INTCPS_SYSCONFIG (gOmapInterruptControllerBase + 0x0010)
61 #define INTCPS_SYSSTATUS (gOmapInterruptControllerBase + 0x0014)
62 #define INTCPS_SIR_IRQ (gOmapInterruptControllerBase + 0x0040)
63 #define INTCPS_SIR_IFQ (gOmapInterruptControllerBase + 0x0044)
64 #define INTCPS_CONTROL (gOmapInterruptControllerBase + 0x0048)
65 #define INTCPS_PROTECTION (gOmapInterruptControllerBase + 0x004C)
66 #define INTCPS_IDLE (gOmapInterruptControllerBase + 0x0050)
67 #define INTCPS_IRQ_PRIORITY (gOmapInterruptControllerBase + 0x0060)
68 #define INTCPS_FIQ_PRIORITY (gOmapInterruptControllerBase + 0x0064)
69 #define INTCPS_THRESHOLD (gOmapInterruptControllerBase + 0x0068)
70 #define INTCPS_ITR(n) (gOmapInterruptControllerBase + 0x0080 + (0x20 * (n)))
71 #define INTCPS_MIR(n) (gOmapInterruptControllerBase + 0x0084 + (0x20 * (n)))
72 #define INTCPS_MIR_CLEAR(n) (gOmapInterruptControllerBase + 0x0088 + (0x20 * (n)))
73 #define INTCPS_MIR_SET(n) (gOmapInterruptControllerBase + 0x008C + (0x20 * (n)))
74 #define INTCPS_ISR_SET(n) (gOmapInterruptControllerBase + 0x0090 + (0x20 * (n)))
75 #define INTCPS_ISR_CLEAR(n) (gOmapInterruptControllerBase + 0x0094 + (0x20 * (n)))
76 #define INTCPS_PENDING_IRQ(n) (gOmapInterruptControllerBase + 0x0098 + (0x20 * (n)))
77 #define INTCPS_PENDING_FIQ(n) (gOmapInterruptControllerBase + 0x009C + (0x20 * (n)))
78 #define INTCPS_ILR(m) (gOmapInterruptControllerBase + 0x0100 + (0x04 * (m)))