1/*
2 * OMAP 35xx support
3 */
4
5#ifndef _PEXPERT_OMAP335X_H_
6#define _PEXPERT_OMAP335X_H_
7
8/*
9 * Note, on older OMAP platforms, the size of the NS16550 UARTS
10 * is different, for this one it's 32-bit.
11 */
12
13#define RBR     0x0
14#define IER     0x4
15#define FCR     0x8
16#define LCR     0xC
17#define MCR     0x10
18#define LSR     0x14            // 335x
19#define MSR     0x18
20#define SCR     0x1C
21#define SSR     0x44            // 335x
22
23#define OMAP3_GIC_BASE           0x48200000
24
25#define OMAP3_L4_WKUP_PERIPH_BASE    0x44C00000
26#define OMAP3_L4_PERIPH_BASE    0x48000000
27#define OMAP3_UART_BASE         (OMAP3_L4_WKUP_PERIPH_BASE + 0x209000)  // This is uart0 (default usb on beaglebone)
28
29#define OMAP3_UART_CLOCK        48000000
30#define OMAP3_UART_BAUDRATE     115200
31
32#define LCR_BKSE	0x80        /* Bank select enable */
33#define LCR_8N1		0x03
34
35#define SSR_TXFIFOFULL	0x01    /* 335x */
36
37#define LSR_DR		0x01        /* Data ready */
38#define LSR_THRE	0x20        /* Xmit holding register empty */
39
40#define MCR_DTR         0x01
41#define MCR_RTS         0x02
42
43#define FCR_FIFO_EN     0x01    /* Fifo enable */
44#define FCR_RXSR        0x02    /* Receiver soft reset */
45#define FCR_TXSR        0x04    /* Transmitter soft reset */
46
47#define LCRVAL LCR_8N1          /* 8 data, 1 stop, no parity */
48#define MCRVAL (MCR_DTR | MCR_RTS)  /* RTS/DTR */
49#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR)  /* Clear & enable FIFOs */
50
51#define THR     RBR
52#define DLL     RBR
53#define DLM     IER
54
55/*
56 * gPIC configuration
57 */
58#define INT_NROF_VECTORS      (96)
59#define MAX_VECTOR            (INT_NROF_VECTORS - 1)
60#define INTCPS_SYSCONFIG      (gOmapInterruptControllerBase + 0x0010)
61#define INTCPS_SYSSTATUS      (gOmapInterruptControllerBase + 0x0014)
62#define INTCPS_SIR_IRQ        (gOmapInterruptControllerBase + 0x0040)
63#define INTCPS_SIR_IFQ        (gOmapInterruptControllerBase + 0x0044)
64#define INTCPS_CONTROL        (gOmapInterruptControllerBase + 0x0048)
65#define INTCPS_PROTECTION     (gOmapInterruptControllerBase + 0x004C)
66#define INTCPS_IDLE           (gOmapInterruptControllerBase + 0x0050)
67#define INTCPS_IRQ_PRIORITY   (gOmapInterruptControllerBase + 0x0060)
68#define INTCPS_FIQ_PRIORITY   (gOmapInterruptControllerBase + 0x0064)
69#define INTCPS_THRESHOLD      (gOmapInterruptControllerBase + 0x0068)
70#define INTCPS_ITR(n)         (gOmapInterruptControllerBase + 0x0080 + (0x20 * (n)))
71#define INTCPS_MIR(n)         (gOmapInterruptControllerBase + 0x0084 + (0x20 * (n)))
72#define INTCPS_MIR_CLEAR(n)   (gOmapInterruptControllerBase + 0x0088 + (0x20 * (n)))
73#define INTCPS_MIR_SET(n)     (gOmapInterruptControllerBase + 0x008C + (0x20 * (n)))
74#define INTCPS_ISR_SET(n)     (gOmapInterruptControllerBase + 0x0090 + (0x20 * (n)))
75#define INTCPS_ISR_CLEAR(n)   (gOmapInterruptControllerBase + 0x0094 + (0x20 * (n)))
76#define INTCPS_PENDING_IRQ(n) (gOmapInterruptControllerBase + 0x0098 + (0x20 * (n)))
77#define INTCPS_PENDING_FIQ(n) (gOmapInterruptControllerBase + 0x009C + (0x20 * (n)))
78#define INTCPS_ILR(m)         (gOmapInterruptControllerBase + 0x0100 + (0x04 * (m)))
79
80/*
81 * Timer.
82 */
83
84#define OMAP3_TIMER0_BASE       (OMAP3_L4_WKUP_PERIPH_BASE + 0x205000)  // 0x44E05000
85
86#define OMAP3_TIMER1_BASE       (OMAP3_L4_WKUP_PERIPH_BASE + 0x231000)  // 0x44E31000
87#define OMAP3_TIMER1_ENAB		0x44E004C4  // CM_WKUP 0x44E0_0400 + CM_WKUP_TIMER1_CLKCTRL    C4h . 0
88
89#define OMAP3_TIMER2_BASE       (OMAP3_L4_PERIPH_BASE + 0x40000)    // 0x48040000
90#define OMAP3_TIMER3_BASE       (OMAP3_L4_PERIPH_BASE + 0x42000)    // 0x48042000
91#define OMAP3_TIMER4_BASE       (OMAP3_L4_PERIPH_BASE + 0x44000)    // 0x48044000
92#define OMAP3_TIMER5_BASE       (OMAP3_L4_PERIPH_BASE + 0x46000)    // 0x48046000
93#define OMAP3_TIMER6_BASE       (OMAP3_L4_PERIPH_BASE + 0x48000)    // 0x48048000
94#define OMAP3_TIMER7_BASE       (OMAP3_L4_PERIPH_BASE + 0x4A000)    // 0x4804A000
95
96#define OMAP3_TIMER0_IRQ		66
97#define OMAP3_TIMER1_IRQ		67
98#define OMAP3_TIMER2_IRQ		68
99#define OMAP3_TIMER3_IRQ		69
100#define OMAP3_TIMER4_IRQ		92
101#define OMAP3_TIMER5_IRQ		93
102#define OMAP3_TIMER6_IRQ		94
103#define OMAP3_TIMER7_IRQ		95
104
105#define OMAP335X_SCH_TIMER		1
106#define OMAP335X_SCH_TIMER_BASE	OMAP3_TIMER1_BASE
107#define OMAP335X_SCH_TIMER_IRQ	OMAP3_TIMER1_IRQ
108
109#ifdef OMAP335X_SCH_TIMER==1
110
111#define TIDR            0x0
112#define TIOCP_CFG       0x10
113#define TISTAT          0x14
114#define TISR            0x18
115#define TIER            0x1C
116#define TWER            0x20
117#define TCLR            0x24
118#define TCRR            0x28
119#define TLDR            0x2C
120#define TTGR            0x30
121#define TWPS            0x34
122#define TMAR            0x38
123#define TCAR1           0x3C
124#define TSICR           0x40
125#define TCAR2           0x44
126
127/* Only for DMTIMER_1MS; Timer1 */
128#define TPIR            0x48
129#define TNIR            0x4C
130#define TCVR            0x50
131#define TOCR            0x54
132#define TOWR            0x58
133
134#else /* OMAP335X_SCH_TIMER != 1 */
135
136#define TIDR            0x0
137#define TIOCP_CFG       0x10
138#define TISTAT          0x28
139#define TISR            0x2C
140#define TIER            0x30
141#define TWER            0x34
142#define TCLR            0x38
143#define TCRR            0x3C
144#define TLDR            0x40
145#define TTGR            0x44
146#define TWPS            0x48
147#define TMAR            0x4C
148#define TCAR1           0x50
149#define TSICR           0x54
150#define TCAR2           0x58
151
152#endif
153
154#endif /* !_PEXPERT_OMAP335X_H_ */
155