| /broadcom-cfe-1.4.2/cfe/dev/ |
| H A D | dev_dp83815.c | 1227 uint16_t control; local
1229 control = mii_read_register(sc, MII_BMCR);
1231 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN);
1232 mii_write_register(sc, MII_BMCR, control);
1233 control &=~ (BMCR_SPEED0 | BMCR_SPEED1 | BMCR_DUPLEX);
1240 control |= BMCR_DUPLEX;
1243 control |= BMCR_SPEED100;
1246 control |= BMCR_SPEED100 | BMCR_DUPLEX ;
1250 mii_write_register(sc, MII_BMCR, control);
1256 uint16_t control, statu local
[all...] |
| H A D | dev_aic6915.c | 377 /* MII polling control */
451 /* PCI control registers */
857 uint16_t control; local
859 control = mii_read_register(sc, sc->phy_addr, MII_BMCR);
861 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN);
862 mii_write_register(sc, sc->phy_addr, MII_BMCR, control);
863 control &=~ (BMCR_SPEED0 | BMCR_SPEED1 | BMCR_DUPLEX);
870 control |= BMCR_DUPLEX;
873 control |= BMCR_SPEED100;
876 control |
886 uint16_t control, status, remote; local
[all...] |
| H A D | dev_i82559.c | 157 tx, space for prefixed control is included in all packet buffers. */
244 /* Head and tail pointers for the tx ring (of transmit control blocks). */
702 /* Allocate tx control blocks */
982 uint16_t control, status, cap; local
996 control = (*sc->mii_read_register)(sc, MII_BMCR);
1002 control = (*sc->mii_read_register)(sc, MII_BMCR);
1003 if ((control && BMCR_RESET) == 0) break;
1008 if ((control & BMCR_RESET) != 0) {
1017 control |= (BMCR_ANENABLE | BMCR_RESTARTAN);
1018 (*sc->mii_write_register)(sc, MII_BMCR, control);
[all...] |
| H A D | dev_tulip.c | 1280 uint16_t control; local
1292 control = mii_read_register(sc, MII_BMCR);
1295 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN);
1296 mii_write_register(sc, MII_BMCR, control);
1297 control &=~ (BMCR_SPEED0 | BMCR_SPEED1 | BMCR_DUPLEX);
1306 control |= BMCR_DUPLEX;
1310 control |= BMCR_SPEED100;
1314 control |= BMCR_SPEED100 | BMCR_DUPLEX ;
1320 mii_write_register(sc, MII_BMCR, control);
1331 uint16_t control, statu local
[all...] |
| H A D | dev_bcm5700.c | 434 /* MII polling control */
465 The 5700 swapping control can deal with this, but for now, just
492 Externally mastered DMA (control and data) uses match-bits and does
529 the offsets of 32-bit fields in control structs (e.g.,
531 control fields are swapped. We deal with this explicitly for
589 /* Some general control registers */
1261 uint16_t control; local
1263 control = mii_read_register(sc, sc->phy_addr, MII_BMCR);
1265 control &= ~(BMCR_ANENABLE | BMCR_RESTARTAN);
1266 mii_write_register(sc, sc->phy_addr, MII_BMCR, control);
1290 uint16_t control, status, remote, xremote; local
[all...] |
| H A D | dev_bcm4401.c | 810 uint16_t control, status, remote; local
822 control = mii_read(sc, MII_BMCR);
|
| /broadcom-cfe-1.4.2/cfe/arch/mips/common/src/ |
| H A D | dev_flash_all.S | 95 li v1,M_SR_IE # master interrupt control
|
| H A D | init_ram.S | 436 li v1,M_SR_IE # master interrupt control
|
| H A D | apientry.S | 174 * Transfer control back to CFE, passing exit status.
191 li t0,M_SR_IE # master interrupt control
|
| H A D | zipstart_init.S | 565 li v1,M_SR_IE # master interrupt control
|
| H A D | init_mips.S | 1045 li v1,M_SR_IE # master interrupt control
|
| /broadcom-cfe-1.4.2/cfe/arch/ppc/chipset/mpc824x/src/ |
| H A D | dev_tulip.c | 270 uint32_t rxdscr_ctrl; /* RDES1 control bits (chaining) */
272 uint32_t txdscr_ctrl; /* TDES1 control bits */
1481 uint16_t control; local
1493 control = (*sc->mii_read_register)(sc, MII_BMCR);
1496 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN);
1497 (*sc->mii_write_register)(sc, MII_BMCR, control);
1498 control &=~ (BMCR_SPEED0 | BMCR_SPEED1 | BMCR_DUPLEX);
1507 control |= BMCR_DUPLEX;
1511 control |= BMCR_SPEED100;
1515 control |
1532 uint16_t control, status, cap; local
[all...] |
| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/ |
| H A D | bcm1480_altcpu.S | 504 # CPU[a0] is back in our control.
606 * and we need to get control of the system again.
|
| /broadcom-cfe-1.4.2/cfe/arch/mips/chipset/bcmsb/src/ |
| H A D | dev_sb_mac.c | 941 uint16_t control, status, remote; local
961 control = mii_read(sc, MII_BMCR);
|