Searched refs:irq (Results 1 - 25 of 102) sorted by relevance

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/barrelfish-2018-10-04/kernel/include/arch/x86/
H A Dpic.h19 bool pic_have_interrupt(int irq);
21 void pic_eoi(int irq);
22 void pic_toggle_irq(int irq, bool enable);
/barrelfish-2018-10-04/lib/devif/backends/net/mlx4/include/linux/
H A Dhardirq.h38 #define synchronize_irq(irq) _intr_drain((irq))
H A Dinterrupt.h52 int irq; member in struct:irq_ent
56 _irq_rid(struct device *dev, int irq) argument
58 if (irq == dev->irq)
60 return irq - dev->msix + 1;
69 irqe->handler(irqe->irq, irqe->arg);
73 _irq_ent(struct device *dev, int irq) argument
78 if (irqe->irq == irq)
85 request_irq(unsigned int irq, irq_handler_ argument
121 bind_irq_to_cpu(unsigned int irq, int cpu_id) argument
138 free_irq(unsigned int irq, void *device) argument
[all...]
/barrelfish-2018-10-04/kernel/arch/x86/
H A Dpic.c25 void pic_eoi(int irq) argument
31 if(irq < 8) {
32 eoi = lpc_pic_ocw2_level_insert(eoi, irq);
35 eoi = lpc_pic_ocw2_level_insert(eoi, irq - 8);
43 bool pic_have_interrupt(int irq) argument
45 if(irq < 8) {
49 return (lpc_pic_master_ocw3rd_rd(&pic) & (1 << irq)) != 0;
52 return (lpc_pic_slave_ocw3rd_rd(&pic) & (1 << (irq -8))) != 0;
141 * \brief Enable/Disable interrupt 'irq'.
147 void pic_toggle_irq(int irq, boo argument
[all...]
/barrelfish-2018-10-04/usr/pci/
H A Dht_config.h22 uint64_t nr_mapped_regions, uint32_t irq);
/barrelfish-2018-10-04/kernel/include/arch/armv8/
H A Dgic_v3.h30 void gic_ack_irq(uint32_t irq); //
31 void gic_raise_softirq(uint8_t cpumask, uint8_t irq); //
H A Dirq.h31 void send_user_interrupt(int irq);
H A Darm_hal.h48 bool pit_handle_irq(uint32_t irq);
/barrelfish-2018-10-04/usr/drivers/xeon_phi/
H A Dinterrupts.c126 if (!phi->irq->msix_enabled) {
129 err = pci_msix_enable(&phi->irq->msix_count);
134 if (!msix_allocator_init(&phi->irq->msix_alloc, phi->irq->msix_count)) {
142 xeon_phi_irq_msi_vector_wr(&phi->irq->irq_registers, 0, val);
144 phi->irq->msix_enabled = 1;
156 phi->irq = calloc(1, sizeof(struct irq_info));
157 if (phi->irq == NULL) {
161 xeon_phi_irq_initialize(&phi->irq->irq_registers, XEON_PHI_MMIO_TO_SBOX(phi));
H A Dinterrupts.h114 xeon_phi_irq_int_enable_wr(&phi->irq->irq_registers, val);
116 phi->irq->irq_enabled = 1;
126 xeon_phi_irq_int_enable_t val = xeon_phi_irq_int_enable_rd(&phi->irq->irq_registers);
127 xeon_phi_irq_int_disable_wr(&phi->irq->irq_registers, val);
129 phi->irq->irq_enabled = 0;
/barrelfish-2018-10-04/usr/kaluga/
H A Dint_caps.c36 errval_t init_int_caps_manager(struct capref irq) argument
38 assert(!capref_is_null(irq));
39 all_irq_cap = irq;
/barrelfish-2018-10-04/kernel/include/arch/arm/
H A Dgic.h38 void gic_ack_irq(uint32_t irq);
39 void gic_raise_softirq(uint8_t cpumask, uint8_t irq);
/barrelfish-2018-10-04/usr/arrakismon/
H A Dapic.h40 void apic_assert_irq (struct apic *a, uint8_t irq);
41 void apic_assert_pic_irq (struct apic *a, uint8_t irq);
H A Dpc16550d.h28 uint8_t irq; member in struct:pc16550d
37 struct pc16550d *pc16550d_new (uint16_t base_port, uint8_t irq, struct lpc *lpc);
H A Dlpc.c52 pic_irq_masked (struct lpc *l, int irq) { argument
53 assert(irq < 16);
57 if (irq > 7 && l->ocw1[0].u.irq_mask & (1 << 2)) {
61 uint8_t rel_irq = irq & 0x7;
62 int ctrlr = irq >> 3;
81 for (int irq = 0; irq < 16; irq++) {
83 if (l->irq_state[irq] == LPC_PIC_IRQ_PENDING) {
84 assert(irq !
129 lpc_pic_assert_irq(struct lpc *l, uint8_t irq) argument
149 int irq = ctrlr << 3; local
161 int irq = l->ocw2[ctrlr].u.irq_lvl_sel | (ctrlr << 3); local
[all...]
/barrelfish-2018-10-04/usr/drivers/serial/
H A Dserial_kernel.c36 if(params->irq == SERIAL_IRQ_INVALID)
37 USER_PANIC("serial_kernel requires an irq= parameter");
40 err = inthandler_setup_arm(serial_interrupt, NULL, params->irq);
H A Dserial_pl011.c46 uint8_t irq= DEFAULT_IRQ; local
47 if(params->irq != SERIAL_IRQ_INVALID)
48 irq= params->irq;
66 err = inthandler_setup_arm(serial_interrupt, NULL, irq);
/barrelfish-2018-10-04/usr/vmkitmon/
H A Dapic.h40 void apic_assert_irq (struct apic *a, uint8_t irq);
41 void apic_assert_pic_irq (struct apic *a, uint8_t irq);
H A Dpc16550d.h46 uint8_t irq; member in struct:pc16550d
57 struct pc16550d *pc16550d_new (uint16_t base_port, uint8_t irq, struct lpc *lpc);
H A Dlpc.c52 pic_irq_masked (struct lpc *l, int irq) { argument
53 assert(irq < 16);
57 if (irq > 7 && l->ocw1[0].u.irq_mask & (1 << 2)) {
61 uint8_t rel_irq = irq & 0x7;
62 int ctrlr = irq >> 3;
81 for (int irq = 0; irq < 16; irq++) {
83 if (l->irq_state[irq] == LPC_PIC_IRQ_PENDING) {
84 assert(irq !
138 lpc_pic_assert_irq(struct lpc *l, uint8_t irq) argument
158 int irq = ctrlr << 3; local
170 int irq = l->ocw2[ctrlr].u.irq_lvl_sel | (ctrlr << 3); local
[all...]
/barrelfish-2018-10-04/kernel/include/arch/armv7/
H A Dirq.h29 void send_user_interrupt(int irq);
/barrelfish-2018-10-04/kernel/include/arch/x86_32/
H A Dmisc.h19 #include <irq.h>
/barrelfish-2018-10-04/kernel/include/arch/x86_64/
H A Dmisc.h19 #include <irq.h>
/barrelfish-2018-10-04/kernel/arch/arm/
H A Dexn.c22 #include <irq.h>
255 uint32_t irq = gic_get_active_irq(); local
256 panic("IRQ %"PRIu32" in the kernel", irq);
316 uint32_t irq = 0; local
317 irq = gic_get_active_irq();
318 debug(SUBSYS_DISPATCH, "IRQ %"PRIu32" while %s\n", irq,
322 if (timer_interrupt(irq)) {
329 else if(irq == 1)
331 gic_ack_irq(irq);
335 gic_ack_irq(irq);
[all...]
/barrelfish-2018-10-04/kernel/arch/armv7/
H A Dplat_a15mpcore.c110 bool timer_interrupt(uint32_t irq) argument
112 if (irq == timerirq) {
113 gic_ack_irq(irq);

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