1/* 2 * Copyright (c) 2010, ETH Zurich. 3 * All rights reserved. 4 * 5 * This file is distributed under the terms in the attached LICENSE file. 6 * If you do not find this file, copies can be found by writing to: 7 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group. 8 */ 9 10#ifndef KERNEL_ARCH_ARM_IRQ_H 11#define KERNEL_ARCH_ARM_IRQ_H 12 13/* 14 * Interrupt controller (Cortex-A9 MPU INTC) with up to 128 interrupt requests 15 */ 16#define NUM_INTR (128+32) 17 18/// Size of hardware IRQ dispatch table == #NIDT - #NEXCEPTIONS exceptions 19#define NDISPATCH (NUM_INTR) 20 21struct capability; 22struct idc_recv_msg; 23//struct sysret irq_table_set(struct capability *to, struct idc_recv_msg *msg); 24//struct sysret irq_table_delete(struct capability *to, struct idc_recv_msg *msg); 25errval_t irq_table_set(unsigned int nidt, capaddr_t endpoint); 26errval_t irq_table_delete(unsigned int nidt); 27struct kcb; 28errval_t irq_table_notify_domains(struct kcb *kcb); 29void send_user_interrupt(int irq); 30 31#endif // KERNEL_ARCH_ARM_IRQ_H 32