/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/omap2/dss/ |
H A D | dss.c | 58 #define REG_FLD_MOD(idx, val, start, end) \ macro 151 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ 155 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ 167 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); 195 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 209 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 271 REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ 288 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ 527 REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1); 543 REG_FLD_MOD(DSS_CONTRO [all...] |
H A D | dispc.c | 145 #define REG_FLD_MOD(idx, val, start, end) \ macro 537 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit); 747 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11); 748 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11); 810 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0); 812 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16); 871 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1); 947 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit); 1028 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); 1175 REG_FLD_MOD(dispc_reg_at [all...] |
H A D | dsi.c | 106 #define REG_FLD_MOD(idx, val, start, end) \ macro 700 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */ 759 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */ 761 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 779 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */ 1020 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ 1055 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ 1390 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27); 1437 REG_FLD_MOD(DSI_CTRL, 1, 0, 0); 1438 REG_FLD_MOD(DSI_CTR [all...] |
H A D | rfbi.c | 67 #define REG_FLD_MOD(idx, val, start, end) \ macro 338 REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0); 451 REG_FLD_MOD(RFBI_CONFIG(rfbi_module), 784 REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/video/omap2/dss/ |
H A D | dss.c | 58 #define REG_FLD_MOD(idx, val, start, end) \ macro 151 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ 155 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ 167 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); 195 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 209 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 271 REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ 288 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ 527 REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1); 543 REG_FLD_MOD(DSS_CONTRO [all...] |
H A D | dispc.c | 145 #define REG_FLD_MOD(idx, val, start, end) \ macro 537 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit); 747 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11); 748 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11); 810 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0); 812 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16); 871 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1); 947 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit); 1028 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); 1175 REG_FLD_MOD(dispc_reg_at [all...] |
H A D | dsi.c | 106 #define REG_FLD_MOD(idx, val, start, end) \ macro 700 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */ 759 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */ 761 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 779 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */ 1020 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ 1055 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ 1390 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27); 1437 REG_FLD_MOD(DSI_CTRL, 1, 0, 0); 1438 REG_FLD_MOD(DSI_CTR [all...] |
H A D | rfbi.c | 67 #define REG_FLD_MOD(idx, val, start, end) \ macro 338 REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0); 451 REG_FLD_MOD(RFBI_CONFIG(rfbi_module), 784 REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
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