Lines Matching refs:REG_FLD_MOD
145 #define REG_FLD_MOD(idx, val, start, end) \
537 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
747 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
748 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
810 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
812 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
871 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
947 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
1028 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1175 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1178 REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1180 REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1182 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1183 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1715 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1726 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1773 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1860 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1867 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1874 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1881 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1905 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1912 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1952 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1954 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1986 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1988 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1998 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2000 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2064 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
3056 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3061 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3076 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);