Lines Matching refs:REG_FLD_MOD
106 #define REG_FLD_MOD(idx, val, start, end) \
700 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
759 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
761 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
779 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
1020 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1055 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1390 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1437 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1438 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1439 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1440 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1535 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1583 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1615 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1716 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1769 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1793 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1812 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1912 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2715 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2747 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2793 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3070 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3073 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3076 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);