Lines Matching refs:REG_FLD_MOD
58 #define REG_FLD_MOD(idx, val, start, end) \
151 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
155 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
167 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
195 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
209 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
271 REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
288 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
527 REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
543 REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
548 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
581 REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
584 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
587 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
588 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
589 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */