1/* 2 * linux/drivers/video/omap2/dss/dss.c 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * Some code and ideas taken from drivers/video/omap/ driver 8 * by Imre Deak. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#define DSS_SUBSYS_NAME "DSS" 24 25#include <linux/kernel.h> 26#include <linux/io.h> 27#include <linux/err.h> 28#include <linux/delay.h> 29#include <linux/interrupt.h> 30#include <linux/seq_file.h> 31#include <linux/clk.h> 32 33#include <plat/display.h> 34#include "dss.h" 35 36#define DSS_BASE 0x48050000 37 38#define DSS_SZ_REGS SZ_512 39 40struct dss_reg { 41 u16 idx; 42}; 43 44#define DSS_REG(idx) ((const struct dss_reg) { idx }) 45 46#define DSS_REVISION DSS_REG(0x0000) 47#define DSS_SYSCONFIG DSS_REG(0x0010) 48#define DSS_SYSSTATUS DSS_REG(0x0014) 49#define DSS_IRQSTATUS DSS_REG(0x0018) 50#define DSS_CONTROL DSS_REG(0x0040) 51#define DSS_SDI_CONTROL DSS_REG(0x0044) 52#define DSS_PLL_CONTROL DSS_REG(0x0048) 53#define DSS_SDI_STATUS DSS_REG(0x005C) 54 55#define REG_GET(idx, start, end) \ 56 FLD_GET(dss_read_reg(idx), start, end) 57 58#define REG_FLD_MOD(idx, val, start, end) \ 59 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) 60 61static struct { 62 void __iomem *base; 63 64 struct clk *dpll4_m4_ck; 65 66 unsigned long cache_req_pck; 67 unsigned long cache_prate; 68 struct dss_clock_info cache_dss_cinfo; 69 struct dispc_clock_info cache_dispc_cinfo; 70 71 enum dss_clk_source dsi_clk_source; 72 enum dss_clk_source dispc_clk_source; 73 74 u32 ctx[DSS_SZ_REGS / sizeof(u32)]; 75} dss; 76 77static int _omap_dss_wait_reset(void); 78 79static inline void dss_write_reg(const struct dss_reg idx, u32 val) 80{ 81 __raw_writel(val, dss.base + idx.idx); 82} 83 84static inline u32 dss_read_reg(const struct dss_reg idx) 85{ 86 return __raw_readl(dss.base + idx.idx); 87} 88 89#define SR(reg) \ 90 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) 91#define RR(reg) \ 92 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) 93 94void dss_save_context(void) 95{ 96 if (cpu_is_omap24xx()) 97 return; 98 99 SR(SYSCONFIG); 100 SR(CONTROL); 101 102#ifdef CONFIG_OMAP2_DSS_SDI 103 SR(SDI_CONTROL); 104 SR(PLL_CONTROL); 105#endif 106} 107 108void dss_restore_context(void) 109{ 110 if (_omap_dss_wait_reset()) 111 DSSERR("DSS not coming out of reset after sleep\n"); 112 113 RR(SYSCONFIG); 114 RR(CONTROL); 115 116#ifdef CONFIG_OMAP2_DSS_SDI 117 RR(SDI_CONTROL); 118 RR(PLL_CONTROL); 119#endif 120} 121 122#undef SR 123#undef RR 124 125void dss_sdi_init(u8 datapairs) 126{ 127 u32 l; 128 129 BUG_ON(datapairs > 3 || datapairs < 1); 130 131 l = dss_read_reg(DSS_SDI_CONTROL); 132 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ 133 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ 134 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ 135 dss_write_reg(DSS_SDI_CONTROL, l); 136 137 l = dss_read_reg(DSS_PLL_CONTROL); 138 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ 139 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ 140 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ 141 dss_write_reg(DSS_PLL_CONTROL, l); 142} 143 144int dss_sdi_enable(void) 145{ 146 unsigned long timeout; 147 148 dispc_pck_free_enable(1); 149 150 /* Reset SDI PLL */ 151 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ 152 udelay(1); /* wait 2x PCLK */ 153 154 /* Lock SDI PLL */ 155 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ 156 157 /* Waiting for PLL lock request to complete */ 158 timeout = jiffies + msecs_to_jiffies(500); 159 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { 160 if (time_after_eq(jiffies, timeout)) { 161 DSSERR("PLL lock request timed out\n"); 162 goto err1; 163 } 164 } 165 166 /* Clearing PLL_GO bit */ 167 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); 168 169 /* Waiting for PLL to lock */ 170 timeout = jiffies + msecs_to_jiffies(500); 171 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { 172 if (time_after_eq(jiffies, timeout)) { 173 DSSERR("PLL lock timed out\n"); 174 goto err1; 175 } 176 } 177 178 dispc_lcd_enable_signal(1); 179 180 /* Waiting for SDI reset to complete */ 181 timeout = jiffies + msecs_to_jiffies(500); 182 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { 183 if (time_after_eq(jiffies, timeout)) { 184 DSSERR("SDI reset timed out\n"); 185 goto err2; 186 } 187 } 188 189 return 0; 190 191 err2: 192 dispc_lcd_enable_signal(0); 193 err1: 194 /* Reset SDI PLL */ 195 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 196 197 dispc_pck_free_enable(0); 198 199 return -ETIMEDOUT; 200} 201 202void dss_sdi_disable(void) 203{ 204 dispc_lcd_enable_signal(0); 205 206 dispc_pck_free_enable(0); 207 208 /* Reset SDI PLL */ 209 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 210} 211 212void dss_dump_clocks(struct seq_file *s) 213{ 214 unsigned long dpll4_ck_rate; 215 unsigned long dpll4_m4_ck_rate; 216 217 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 218 219 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); 220 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); 221 222 seq_printf(s, "- DSS -\n"); 223 224 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); 225 226 if (cpu_is_omap3630()) 227 seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n", 228 dpll4_ck_rate, 229 dpll4_ck_rate / dpll4_m4_ck_rate, 230 dss_clk_get_rate(DSS_CLK_FCK1)); 231 else 232 seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n", 233 dpll4_ck_rate, 234 dpll4_ck_rate / dpll4_m4_ck_rate, 235 dss_clk_get_rate(DSS_CLK_FCK1)); 236 237 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 238} 239 240void dss_dump_regs(struct seq_file *s) 241{ 242#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) 243 244 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); 245 246 DUMPREG(DSS_REVISION); 247 DUMPREG(DSS_SYSCONFIG); 248 DUMPREG(DSS_SYSSTATUS); 249 DUMPREG(DSS_IRQSTATUS); 250 DUMPREG(DSS_CONTROL); 251 DUMPREG(DSS_SDI_CONTROL); 252 DUMPREG(DSS_PLL_CONTROL); 253 DUMPREG(DSS_SDI_STATUS); 254 255 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); 256#undef DUMPREG 257} 258 259void dss_select_dispc_clk_source(enum dss_clk_source clk_src) 260{ 261 int b; 262 263 BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK && 264 clk_src != DSS_SRC_DSS1_ALWON_FCLK); 265 266 b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; 267 268 if (clk_src == DSS_SRC_DSI1_PLL_FCLK) 269 dsi_wait_dsi1_pll_active(); 270 271 REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ 272 273 dss.dispc_clk_source = clk_src; 274} 275 276void dss_select_dsi_clk_source(enum dss_clk_source clk_src) 277{ 278 int b; 279 280 BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK && 281 clk_src != DSS_SRC_DSS1_ALWON_FCLK); 282 283 b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; 284 285 if (clk_src == DSS_SRC_DSI2_PLL_FCLK) 286 dsi_wait_dsi2_pll_active(); 287 288 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ 289 290 dss.dsi_clk_source = clk_src; 291} 292 293enum dss_clk_source dss_get_dispc_clk_source(void) 294{ 295 return dss.dispc_clk_source; 296} 297 298enum dss_clk_source dss_get_dsi_clk_source(void) 299{ 300 return dss.dsi_clk_source; 301} 302 303/* calculate clock rates using dividers in cinfo */ 304int dss_calc_clock_rates(struct dss_clock_info *cinfo) 305{ 306 unsigned long prate; 307 308 if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) || 309 cinfo->fck_div == 0) 310 return -EINVAL; 311 312 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); 313 314 cinfo->fck = prate / cinfo->fck_div; 315 316 return 0; 317} 318 319int dss_set_clock_div(struct dss_clock_info *cinfo) 320{ 321 unsigned long prate; 322 int r; 323 324 if (cpu_is_omap34xx()) { 325 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); 326 DSSDBG("dpll4_m4 = %ld\n", prate); 327 328 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); 329 if (r) 330 return r; 331 } 332 333 DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); 334 335 return 0; 336} 337 338int dss_get_clock_div(struct dss_clock_info *cinfo) 339{ 340 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1); 341 342 if (cpu_is_omap34xx()) { 343 unsigned long prate; 344 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); 345 if (cpu_is_omap3630()) 346 cinfo->fck_div = prate / (cinfo->fck); 347 else 348 cinfo->fck_div = prate / (cinfo->fck / 2); 349 } else { 350 cinfo->fck_div = 0; 351 } 352 353 return 0; 354} 355 356unsigned long dss_get_dpll4_rate(void) 357{ 358 if (cpu_is_omap34xx()) 359 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); 360 else 361 return 0; 362} 363 364int dss_calc_clock_div(bool is_tft, unsigned long req_pck, 365 struct dss_clock_info *dss_cinfo, 366 struct dispc_clock_info *dispc_cinfo) 367{ 368 unsigned long prate; 369 struct dss_clock_info best_dss; 370 struct dispc_clock_info best_dispc; 371 372 unsigned long fck; 373 374 u16 fck_div; 375 376 int match = 0; 377 int min_fck_per_pck; 378 379 prate = dss_get_dpll4_rate(); 380 381 fck = dss_clk_get_rate(DSS_CLK_FCK1); 382 if (req_pck == dss.cache_req_pck && 383 ((cpu_is_omap34xx() && prate == dss.cache_prate) || 384 dss.cache_dss_cinfo.fck == fck)) { 385 DSSDBG("dispc clock info found from cache.\n"); 386 *dss_cinfo = dss.cache_dss_cinfo; 387 *dispc_cinfo = dss.cache_dispc_cinfo; 388 return 0; 389 } 390 391 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; 392 393 if (min_fck_per_pck && 394 req_pck * min_fck_per_pck > DISPC_MAX_FCK) { 395 DSSERR("Requested pixel clock not possible with the current " 396 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " 397 "the constraint off.\n"); 398 min_fck_per_pck = 0; 399 } 400 401retry: 402 memset(&best_dss, 0, sizeof(best_dss)); 403 memset(&best_dispc, 0, sizeof(best_dispc)); 404 405 if (cpu_is_omap24xx()) { 406 struct dispc_clock_info cur_dispc; 407 fck = dss_clk_get_rate(DSS_CLK_FCK1); 408 fck_div = 1; 409 410 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); 411 match = 1; 412 413 best_dss.fck = fck; 414 best_dss.fck_div = fck_div; 415 416 best_dispc = cur_dispc; 417 418 goto found; 419 } else if (cpu_is_omap34xx()) { 420 for (fck_div = (cpu_is_omap3630() ? 32 : 16); 421 fck_div > 0; --fck_div) { 422 struct dispc_clock_info cur_dispc; 423 424 if (cpu_is_omap3630()) 425 fck = prate / fck_div; 426 else 427 fck = prate / fck_div * 2; 428 429 if (fck > DISPC_MAX_FCK) 430 continue; 431 432 if (min_fck_per_pck && 433 fck < req_pck * min_fck_per_pck) 434 continue; 435 436 match = 1; 437 438 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); 439 440 if (abs(cur_dispc.pck - req_pck) < 441 abs(best_dispc.pck - req_pck)) { 442 443 best_dss.fck = fck; 444 best_dss.fck_div = fck_div; 445 446 best_dispc = cur_dispc; 447 448 if (cur_dispc.pck == req_pck) 449 goto found; 450 } 451 } 452 } else { 453 BUG(); 454 } 455 456found: 457 if (!match) { 458 if (min_fck_per_pck) { 459 DSSERR("Could not find suitable clock settings.\n" 460 "Turning FCK/PCK constraint off and" 461 "trying again.\n"); 462 min_fck_per_pck = 0; 463 goto retry; 464 } 465 466 DSSERR("Could not find suitable clock settings.\n"); 467 468 return -EINVAL; 469 } 470 471 if (dss_cinfo) 472 *dss_cinfo = best_dss; 473 if (dispc_cinfo) 474 *dispc_cinfo = best_dispc; 475 476 dss.cache_req_pck = req_pck; 477 dss.cache_prate = prate; 478 dss.cache_dss_cinfo = best_dss; 479 dss.cache_dispc_cinfo = best_dispc; 480 481 return 0; 482} 483 484 485 486static irqreturn_t dss_irq_handler_omap2(int irq, void *arg) 487{ 488 dispc_irq_handler(); 489 490 return IRQ_HANDLED; 491} 492 493static irqreturn_t dss_irq_handler_omap3(int irq, void *arg) 494{ 495 u32 irqstatus; 496 497 irqstatus = dss_read_reg(DSS_IRQSTATUS); 498 499 if (irqstatus & (1<<0)) /* DISPC_IRQ */ 500 dispc_irq_handler(); 501#ifdef CONFIG_OMAP2_DSS_DSI 502 if (irqstatus & (1<<1)) /* DSI_IRQ */ 503 dsi_irq_handler(); 504#endif 505 506 return IRQ_HANDLED; 507} 508 509static int _omap_dss_wait_reset(void) 510{ 511 int t = 0; 512 513 while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) { 514 if (++t > 1000) { 515 DSSERR("soft reset failed\n"); 516 return -ENODEV; 517 } 518 udelay(1); 519 } 520 521 return 0; 522} 523 524static int _omap_dss_reset(void) 525{ 526 /* Soft reset */ 527 REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1); 528 return _omap_dss_wait_reset(); 529} 530 531void dss_set_venc_output(enum omap_dss_venc_type type) 532{ 533 int l = 0; 534 535 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) 536 l = 0; 537 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) 538 l = 1; 539 else 540 BUG(); 541 542 /* venc out selection. 0 = comp, 1 = svideo */ 543 REG_FLD_MOD(DSS_CONTROL, l, 6, 6); 544} 545 546void dss_set_dac_pwrdn_bgz(bool enable) 547{ 548 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ 549} 550 551int dss_init(bool skip_init) 552{ 553 int r; 554 u32 rev; 555 556 dss.base = ioremap(DSS_BASE, DSS_SZ_REGS); 557 if (!dss.base) { 558 DSSERR("can't ioremap DSS\n"); 559 r = -ENOMEM; 560 goto fail0; 561 } 562 563 if (!skip_init) { 564 /* disable LCD and DIGIT output. This seems to fix the synclost 565 * problem that we get, if the bootloader starts the DSS and 566 * the kernel resets it */ 567 omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); 568 569 /* We need to wait here a bit, otherwise we sometimes start to 570 * get synclost errors, and after that only power cycle will 571 * restore DSS functionality. I have no idea why this happens. 572 * And we have to wait _before_ resetting the DSS, but after 573 * enabling clocks. 574 */ 575 msleep(50); 576 577 _omap_dss_reset(); 578 } 579 580 /* autoidle */ 581 REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); 582 583 /* Select DPLL */ 584 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); 585 586#ifdef CONFIG_OMAP2_DSS_VENC 587 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ 588 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ 589 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ 590#endif 591 592 r = request_irq(INT_24XX_DSS_IRQ, 593 cpu_is_omap24xx() 594 ? dss_irq_handler_omap2 595 : dss_irq_handler_omap3, 596 0, "OMAP DSS", NULL); 597 598 if (r < 0) { 599 DSSERR("omap2 dss: request_irq failed\n"); 600 goto fail1; 601 } 602 603 if (cpu_is_omap34xx()) { 604 dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); 605 if (IS_ERR(dss.dpll4_m4_ck)) { 606 DSSERR("Failed to get dpll4_m4_ck\n"); 607 r = PTR_ERR(dss.dpll4_m4_ck); 608 goto fail2; 609 } 610 } 611 612 dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK; 613 dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; 614 615 dss_save_context(); 616 617 rev = dss_read_reg(DSS_REVISION); 618 printk(KERN_INFO "OMAP DSS rev %d.%d\n", 619 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 620 621 return 0; 622 623fail2: 624 free_irq(INT_24XX_DSS_IRQ, NULL); 625fail1: 626 iounmap(dss.base); 627fail0: 628 return r; 629} 630 631void dss_exit(void) 632{ 633 if (cpu_is_omap34xx()) 634 clk_put(dss.dpll4_m4_ck); 635 636 free_irq(INT_24XX_DSS_IRQ, NULL); 637 638 iounmap(dss.base); 639} 640