Searched refs:channels (Results 76 - 100 of 1485) sorted by path

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/linux-master/drivers/dma/
H A Dacpi-dma.c353 pdata->dma_spec.chan_id = dma->channels;
H A Daltera-msgdma.c872 INIT_LIST_HEAD(&dma_dev->channels);
888 list_add_tail(&mdev->dmachan.device_node, &dma_dev->channels);
H A Damba-pl08x.c17 * The PL080 has 8 channels available for simultaneous use, and the PL081
18 * has only two channels. So on these DMA controllers the number of channels
99 * @channels: the number of channels available in this variant
103 * channels have Nomadik security extension bits that need to be checked
113 u8 channels; member in struct:vendor_data
138 * struct pl08x_phy_chan - holder for the physical channels
223 * channel to become available (only pertains to memcpy channels)
271 * @phy_chans: array of data for the physical channels
2361 pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, struct dma_device *dmadev, unsigned int channels, bool slave) argument
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H A Dapple-admac.c133 struct admac_chan channels[] __counted_by(nchannels);
595 return dma_get_slave_channel(&ad->channels[index].chan);
645 struct admac_chan *adchan = &ad->channels[channo];
809 err = of_property_read_u32(np, "dma-channels", &nchannels);
811 dev_err(&pdev->dev, "missing or invalid dma-channels property\n");
815 ad = devm_kzalloc(&pdev->dev, struct_size(ad, channels, nchannels), GFP_KERNEL);
875 INIT_LIST_HEAD(&dma->channels);
877 struct admac_chan *adchan = &ad->channels[i];
886 list_add_tail(&adchan->chan.device_node, &dma->channels);
H A Dat_hdmac.c342 * @all_chan_mask: all channels availlable in a mask
345 * @chan: channels table to store at_dma_chan structures
357 /* AT THE END channels table */
513 * @nr_channels: Number of channels supported by hardware (max 8)
1933 /* confirm that all channels are disabled */
2018 /* initialize channels related values */
2019 INIT_LIST_HEAD(&atdma->dma_device.channels);
2072 dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s), %d channels\n",
2127 list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels,
2150 list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels,
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H A Dat_xdmac.c441 if (!list_empty(&atxdmac->dma.channels) && suspend_descriptors) {
442 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels,
2134 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2154 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2205 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2211 * Resume only channels not explicitly paused by
2224 * suspend state of channels set though dmaengine API.
2276 * Read number of xdmac channels, read helper function can't be used
2278 * of channels to do the allocation.
2283 dev_err(&pdev->dev, "invalid number of channels (
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H A Dbcm-sba-raid.c22 * except submitting request to SBA hardware device via mailbox channels.
25 * For having more SBA DMA channels, we can create more SBA device nodes
138 /* Maibox client and Mailbox channels */
214 * mailbox channels hoping few active requests
1593 INIT_LIST_HEAD(&dma_dev->channels);
1594 list_add_tail(&sba->dma_chan.device_node, &dma_dev->channels);
1628 /* Number of mailbox channels should be atleast 1 */
H A Dbcm2835-dma.c158 /* shared registers for all dma channels */
167 /* Valid only for channels 0 - 14, 15 has its own base address */
171 /* the max dma length for different channels */
177 /* lite and normal channels have different max frame length */
749 /* non-lite channels can write zeroes w/o accessing memory */
846 list_for_each_entry_safe(c, next, &od->ddev.channels,
931 INIT_LIST_HEAD(&od->ddev.channels);
954 /* skip masked out channels */
978 /* skip channels without irq */
982 /* check if there are other channels tha
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H A Ddma-axi-dmac.c38 * The number of channels and the type of the channel interfaces is selected at
892 of_channels = of_get_child_by_name(dev->of_node, "adi,channels");
1068 INIT_LIST_HEAD(&dma_dev->channels);
H A Ddma-jz4780.c748 /* Clear halt and address error status of all channels. */
909 of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels",
945 * Enable DMA controller, mark all channels as not programmable.
955 INIT_LIST_HEAD(&dd->channels);
H A Ddmaengine.c26 * Each device has a channels list, which runs unlocked but is never modified
88 list_for_each_entry(chan, &dma_dev->channels, device_node) {
108 seq_printf(s, "dma%d (%s): number of channels: %u\n",
314 * If some channels are close to the given CPU, the one with the lowest
331 list_for_each_entry(chan, &device->channels, device_node) {
353 * dma_channel_rebalance - redistribute the available channels
357 * multi-tasking channels) in the non-SMP case.
376 list_for_each_entry(chan, &device->channels, device_node)
384 /* redistribute available channels */
552 * dma_issue_pending_all - flush all pending operations across all channels
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H A Ddmatest.c44 "Maximum number of channels to use (default: all)");
102 * @max_channels: maximum number of channels to use
134 * @channels: channels under test
135 * @nr_channels: number of channels under test
145 struct list_head channels; member in struct:dmatest_info
151 .channels = LIST_HEAD_INIT(test_info.channels),
256 list_for_each_entry(dtc, &info->channels, node) {
272 list_for_each_entry(dtc, &info->channels, nod
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H A Dep93xx_dma.c161 * necessary channel configuration information. For memcpy channels this must
195 * @num_channels: number of channels for this instance
196 * @channels: array of channels
198 * There is one instance of this struct for the M2P channels and one for the
199 * M2M channels. hw_xxx() methods are used to perform operations which are
200 * different on M2M and M2P channels. These methods are called with channel
216 struct ep93xx_dma_chan channels[] __counted_by(num_channels);
579 * For memcpy channels the software trigger must be asserted
1325 edma = kzalloc(struct_size(edma, channels, pdat
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H A Dfsl-edma-common.c848 &dmadev->channels, vchan.chan.device_node) {
855 * On the 32 channels Vybrid/mpc577x edma version, register offsets are
856 * different compared to ColdFire mcf5441x 64 channels edma.
H A Dfsl-edma-main.c109 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
144 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels,
271 * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
447 ret = of_property_read_u32(np, "dma-channels", &chans);
449 dev_err(&pdev->dev, "Can't get dma-channels.\n");
530 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
H A Dfsl-qdma.c1126 ret = of_property_read_u32(np, "dma-channels", &chans);
1128 dev_err(&pdev->dev, "Can't get dma-channels.\n");
1205 INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
1262 &dmadev->channels, vchan.chan.device_node) {
H A Dfsl_raid.c784 INIT_LIST_HEAD(&dma_dev->channels);
H A Dfsldma.c156 * BWC - Bandwidth sharing among channels
1140 * of its channels, report the bug
1149 dev_err(fdev->dev, "too many channels for device\n");
1191 list_add_tail(&chan->common.device_node, &fdev->common.channels);
1228 INIT_LIST_HEAD(&fdev->common.channels);
H A Dhisi_dma.c773 /* This function enables all hw channels in a device */
836 INIT_LIST_HEAD(&dma_dev->channels);
943 dev_info(&hdma_dev->pdev->dev, "fail to create debugfs for channels!\n");
/linux-master/drivers/dma/dw-axi-dmac/
H A Ddw-axi-dmac-platform.c588 /* 64 bit write should handle for 8 channels */
1159 /* Disable DMAC interrupts. We'll enable them after processing channels */
1384 ret = device_property_read_u32(dev, "dma-channels", &tmp);
1523 INIT_LIST_HEAD(&dw->dma.channels);
1601 dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
1636 list_for_each_entry_safe(chan, _chan, &dw->dma.channels,
/linux-master/drivers/dma/dw-edma/
H A Ddw-edma-core.c723 INIT_LIST_HEAD(&dma->channels);
851 /* Common IRQ shared among all channels */
865 /* Distribute IRQs equally among all channels */
947 /* Allocate channels */
964 /* Setup write/read channels */
1004 list_for_each_entry_safe(chan, _chan, &dw->dma.channels,
/linux-master/drivers/dma/dw/
H A Dcore.c772 /* permit channels in accordance with the channels mask */
773 if (dws->channels && !(dws->channels & dwc->mask))
1148 INIT_LIST_HEAD(&dw->dma.channels);
1156 &dw->dma.channels);
1158 list_add(&dwc->chan.device_node, &dw->dma.channels);
1213 /* Clear all interrupts on all channels. */
1252 * across all of the device channels, so we set the maximum segment
1261 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\
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H A Dof.c33 slave.channels = dma_spec->args[3];
39 slave.channels >= BIT(dw->pdata->nr_channels)))
62 if (of_property_read_u32(np, "dma-channels", &nr_channels))
/linux-master/drivers/dma/fsl-dpaa2-qdma/
H A Ddpaa2-qdma.c641 INIT_LIST_HEAD(&dpaa2_qdma->dma_dev.channels);
/linux-master/drivers/dma/hsu/
H A Dhsu.c448 INIT_LIST_HEAD(&hsu->dma.channels);
488 dev_info(chip->dev, "Found HSU DMA, %d channels\n", hsu->nr_channels);

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