Searched refs:pl (Results 51 - 75 of 136) sorted by relevance

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/linux-master/drivers/atm/
H A Dnicstar.c2478 pool_levels pl; local
2486 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2488 switch (pl.buftype) {
2490 pl.count =
2492 pl.level.min = card->sbnr.min;
2493 pl.level.init = card->sbnr.init;
2494 pl.level.max = card->sbnr.max;
2498 pl.count =
2500 pl.level.min = card->lbnr.min;
2501 pl
[all...]
/linux-master/drivers/media/platform/qcom/venus/
H A Dhelpers.c850 v4l2_id_profile_level(u32 hfi_codec, struct hfi_profile_level *pl, u32 *profile, u32 *level) argument
852 u32 hfi_pf = pl->profile;
853 u32 hfi_lvl = pl->level;
886 hfi_id_profile_level(u32 hfi_codec, u32 v4l2_pf, u32 v4l2_lvl, struct hfi_profile_level *pl) argument
890 pl->profile = find_hfi_id(v4l2_pf, h264_profiles, ARRAY_SIZE(h264_profiles));
891 pl->level = find_hfi_id(v4l2_lvl, h264_levels, ARRAY_SIZE(h264_levels));
894 pl->profile = find_hfi_id(v4l2_pf, mpeg2_profiles, ARRAY_SIZE(mpeg2_profiles));
895 pl->level = find_hfi_id(v4l2_lvl, mpeg2_levels, ARRAY_SIZE(mpeg2_levels));
898 pl->profile = find_hfi_id(v4l2_pf, mpeg4_profiles, ARRAY_SIZE(mpeg4_profiles));
899 pl
937 struct hfi_profile_level pl; local
[all...]
/linux-master/drivers/net/wireless/purelifi/plfxlc/
H A Dusb.c828 struct plfxlc_usb *pl = get_plfxlc_usb(interface); local
829 struct plfxlc_mac *mac = plfxlc_usb_to_mac(pl);
831 if (!pl)
833 if (pl->initialized == 0)
835 pl->was_running = test_bit(PURELIFI_DEVICE_RUNNING, &mac->flags);
836 plfxlc_usb_stop(pl);
842 struct plfxlc_usb *pl = get_plfxlc_usb(interface); local
844 if (!pl)
846 if (pl->was_running)
847 plfxlc_usb_resume(pl);
[all...]
/linux-master/drivers/gpu/drm/radeon/
H A Dtrinity_dpm.c667 struct trinity_pl *pl, u32 index)
674 trinity_set_divider_value(rdev, index, pl->sclk);
675 trinity_set_vid(rdev, index, pl->vddc_index);
676 trinity_set_ss_dividers(rdev, index, pl->ss_divider_index);
677 trinity_set_ds_dividers(rdev, index, pl->ds_divider_index);
678 trinity_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
679 trinity_set_force_nbp_state(rdev, index, pl->force_nbp_state);
680 trinity_set_display_wm(rdev, index, pl->display_wm);
681 trinity_set_vce_wm(rdev, index, pl->vce_wm);
1665 struct trinity_pl *pl local
666 trinity_program_power_level(struct radeon_device *rdev, struct trinity_pl *pl, u32 index) argument
1975 struct trinity_pl *pl = &ps->levels[i]; local
1989 struct trinity_pl *pl; local
2010 struct trinity_pl *pl; local
[all...]
H A Dbtc_dpm.c1241 struct rv7xx_pl *pl)
1244 if ((pl->mclk == 0) || (pl->sclk == 0))
1247 if (pl->mclk == pl->sclk)
1250 if (pl->mclk > pl->sclk) {
1251 if (((pl->mclk + (pl->sclk - 1)) / pl
1239 btc_adjust_clock_combinations(struct radeon_device *rdev, const struct radeon_clock_and_voltage_limits *max_limits, struct rv7xx_pl *pl) argument
2711 struct rv7xx_pl *pl; local
2736 struct rv7xx_pl *pl; local
2759 struct rv7xx_pl *pl; local
[all...]
H A Dcypress_dpm.c679 struct rv7xx_pl *pl,
689 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
690 level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
691 level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
694 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
700 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
710 if (pl->mclk > pi->mclk_edc_enable_threshold)
713 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
716 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
719 if (cypress_get_mclk_frequency_ratio(rdev, pl
678 cypress_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, RV770_SMC_HW_PERFORMANCE_LEVEL *level, u8 watermark_level) argument
830 cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_Evergreen_MCRegisterSet *mc_reg_table_data) argument
[all...]
H A Dsi_dpm.c1690 struct rv7xx_pl *pl,
4229 struct rv7xx_pl *pl,
4237 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4240 pl->sclk,
4241 pl->mclk);
4574 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4603 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4696 if (ulv->supported && ulv->pl.vddc) {
4915 struct rv7xx_pl *pl,
4930 level->gen2PCIE = (u8)pl
4228 si_populate_memory_timing_parameters(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) argument
4914 si_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) argument
5553 si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_SIslands_MCRegisterSet *mc_reg_table_data) argument
6677 struct rv7xx_pl *pl = &ps->performance_levels[index]; local
7034 struct rv7xx_pl *pl; local
7054 struct rv7xx_pl *pl; local
7072 struct rv7xx_pl *pl; local
[all...]
H A Dsi_dpm.h140 struct rv7xx_pl pl; member in struct:si_ulv_param
/linux-master/arch/mips/kernel/
H A Dpm-cps.c186 static void cps_gen_cache_routine(u32 **pp, struct uasm_label **pl, argument
209 uasm_build_label(pl, *pp, lbl);
230 static int cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl, argument
286 uasm_build_label(pl, *pp, lbl);
323 static void cps_gen_set_top_bit(u32 **pp, struct uasm_label **pl, argument
328 uasm_build_label(pl, *pp, lbl);
/linux-master/lib/crypto/mpi/
H A Dlonglong.h154 #define umul_ppmm(ph, pl, m0, m1) \
158 (pl) = __m0 * __m1; \
281 #define umul_ppmm(ph, pl, m0, m1) \
284 "=r" ((USItype)(pl)) \
786 #define umul_ppmm(ph, pl, m0, m1) \
793 (pl) = __m0 * __m1; \
796 #define smul_ppmm(ph, pl, m0, m1) \
803 (pl) = __m0 * __m1; \
892 #define umul_ppmm(ph, pl, m0, m1) \
917 "=r" ((USItype)(pl)) \
[all...]
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c1842 struct rv7xx_pl *pl,
3284 struct rv7xx_pl *pl)
3287 if ((pl->mclk == 0) || (pl->sclk == 0))
3290 if (pl->mclk == pl->sclk)
3293 if (pl->mclk > pl->sclk) {
3294 if (((pl->mclk + (pl
3282 btc_adjust_clock_combinations(struct amdgpu_device *adev, const struct amdgpu_clock_and_voltage_limits *max_limits, struct rv7xx_pl *pl) argument
4751 si_populate_memory_timing_parameters(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) argument
5460 si_convert_power_level_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) argument
6090 si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCRegisterSet *mc_reg_table_data) argument
7188 struct rv7xx_pl *pl = &ps->performance_levels[index]; local
7533 struct rv7xx_pl *pl; local
7923 struct rv7xx_pl *pl; local
[all...]
/linux-master/arch/arc/lib/
H A Dstrchr-700.S98 mov.pl r0,0
123 add.pl r3,r3,1
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.h113 u32 pl; member in struct:gk20a_pll
H A Dgm20b.c141 static u32 pl_to_div(u32 pl) argument
143 return pl;
389 u32 old = cur_pll.base.pl;
390 u32 new = pll->pl;
399 cur_pll.base.pl = min(old | BIT(ffs(new) - 1),
404 cur_pll.base.pl = new;
442 if (pll->m == cur_pll.m && pll->pl == cur_pll.pl)
505 pll->pl = DIV_ROUND_UP(nmin * parent_rate, pll->m * rate);
/linux-master/Documentation/userspace-api/media/
H A DMakefile6 PARSER = $(srctree)/Documentation/sphinx/parse-headers.pl
/linux-master/net/dsa/
H A Dport.c232 if (dp->pl)
233 phylink_start(dp->pl);
254 if (dp->pl)
255 phylink_stop(dp->pl);
1667 struct phylink *pl; local
1688 pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn),
1690 if (IS_ERR(pl)) {
1691 pr_err("error creating PHYLINK: %ld\n", PTR_ERR(pl));
1692 return PTR_ERR(pl);
1695 dp->pl
[all...]
/linux-master/drivers/s390/scsi/
H A Dzfcp_qdio.c120 void *pl[ZFCP_QDIO_MAX_SBALS_PER_REQ + 1]; local
125 memset(pl, 0,
136 pl[sbal_no] = qdio->res_q[sbal_idx];
138 zfcp_dbf_hba_def_err(adapter, req_id, scount, pl);
/linux-master/arch/powerpc/include/asm/
H A Dsfp-machine.h265 #define umul_ppmm(ph, pl, m0, m1) \
269 (pl) = __m0 * __m1; \
/linux-master/drivers/ata/
H A Dpata_legacy.c1216 struct legacy_probe *pl = &probe_list[0]; local
1261 for (i = 0; i < NR_HOST; i++, pl++) {
1262 if (pl->port == 0)
1264 if (pl->type == UNKNOWN)
1265 pl->type = probe_chip_type(pl);
1266 pl->slot = slot++;
1267 if (legacy_init_one(pl) == 0)
/linux-master/arch/arm64/crypto/
H A DMakefile87 $(obj)/%-core.S: $(src)/%-armv8.pl
90 $(obj)/sha256-core.S: $(src)/sha512-armv8.pl
/linux-master/scripts/
H A DMakefile.vmlinux_o20 .tmp_initcalls.lds: $(srctree)/scripts/generate_initcall_order.pl \
/linux-master/drivers/staging/media/ipu3/
H A Dipu3-css-params.c1236 * pl (0)
1237 * pl (1)
1240 * pl (2)
1242 * pl (3)
1443 * pl (0)
1444 * pl (1) eoc
1446 * pl (2) - rest of image, if applicable)
1456 * pl(0) eoc
1470 * pl (0) first
1471 * pl (
1494 imgu_css_acc_process_lines(const struct process_lines *pl, struct imgu_abi_acc_operation *p_op, struct imgu_abi_acc_process_lines_cmd_data *p_pl, struct imgu_abi_acc_transfer_op_data *p_tr) argument
1640 struct process_lines pl = { local
1667 struct process_lines pl = { local
1694 struct process_lines pl = { local
[all...]
/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_bo.c442 struct ttm_place *pl = nvbo->placements; local
448 pl[*n].mem_type = TTM_PL_VRAM;
449 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_VRAM ?
454 pl[*n].mem_type = TTM_PL_TT;
455 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_GART ?
460 pl[*n].mem_type = TTM_PL_SYSTEM;
461 pl[*n].flags = busy & NOUVEAU_GEM_DOMAIN_CPU ?
795 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) argument
809 *pl = nvbo->placement;
/linux-master/arch/arm64/lib/
H A Dstrnlen.S82 ccmp tmp1, #0, #0, pl /* NZCV = 0000 */
/linux-master/tools/testing/selftests/kselftest/
H A Drunner.sh32 "$BASE_DIR"/kselftest/prefix.pl

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