Searched refs:parents (Results 51 - 75 of 179) sorted by relevance

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/linux-master/drivers/gpio/
H A Dgpio-xlp.c288 girq->parents = devm_kcalloc(&pdev->dev, 1,
289 sizeof(*girq->parents),
291 if (!girq->parents)
293 girq->parents[0] = irq;
H A Dgpio-hlwd.c289 girq->parents = devm_kcalloc(&pdev->dev, 1,
290 sizeof(*girq->parents),
292 if (!girq->parents)
294 girq->parents[0] = hlwd->irq;
H A Dgpio-ath79.c285 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
287 if (!girq->parents)
289 girq->parents[0] = platform_get_irq(pdev, 0);
H A Dgpio-tqmx86.c309 girq->parents = devm_kcalloc(&pdev->dev, 1,
310 sizeof(*girq->parents),
312 if (!girq->parents) {
316 girq->parents[0] = irq;
H A Dgpio-altera.c300 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
302 if (!girq->parents)
306 girq->parents[0] = altera_gc->mapped_irq;
H A Dgpio-cadence.c232 girq->parents = devm_kcalloc(&pdev->dev, 1,
233 sizeof(*girq->parents),
235 if (!girq->parents) {
239 girq->parents[0] = irq;
H A Dgpio-ftgpio010.c294 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
296 if (!girq->parents) {
302 girq->parents[0] = irq;
H A Dgpio-realtek-otto.c422 girq->parents = devm_kcalloc(dev, girq->num_parents,
423 sizeof(*girq->parents), GFP_KERNEL);
424 if (!girq->parents)
426 girq->parents[0] = irq;
H A Dgpio-pl061.c350 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
352 if (!girq->parents)
354 girq->parents[0] = irq;
H A Dgpio-vf610.c377 girq->parents = devm_kcalloc(&pdev->dev, 1,
378 sizeof(*girq->parents),
380 if (!girq->parents)
382 girq->parents[0] = port->irq;
/linux-master/drivers/clk/sunxi/
H A Dclk-sun4i-tcon-ch1.c226 const char *parents[TCON_CH1_SCLK2_PARENTS]; local
243 ret = of_clk_parent_fill(node, parents, TCON_CH1_SCLK2_PARENTS);
245 pr_err("%s Could not retrieve the parents\n", clk_name);
255 init.parent_names = parents;
H A Dclk-sun9i-cpus.c187 const char *parents[SUN9I_CPUS_MAX_PARENTS]; local
204 /* we have a mux, we will have >1 parents */
205 ret = of_clk_parent_fill(node, parents, SUN9I_CPUS_MAX_PARENTS);
218 clk = clk_register_composite(NULL, clk_name, parents, ret,
H A Dclk-factors.c22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
188 const char *parents[FACTORS_MAX_PARENTS]; local
191 /* if we have a mux, we will have >1 parents */
192 i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS);
246 parents, i,
/linux-master/tools/cgroup/
H A Diocost_coef_gen.py67 parents = glob.glob('/sys/block/*/' + devname)
68 if len(parents):
69 devname = os.path.basename(os.path.dirname(parents[0]))
/linux-master/scripts/
H A Ddev-needs.sh15 parents) of these devices. It does a breadth first search of the dependency
43 --exclude-parents Don't follow parent devices when tracking probe
243 --exclude-parents)
/linux-master/tools/hv/
H A Dvmbus_testing310 parents = [state_parser, path_parser],
338 parents = [path_parser], prog = "vmbus_testing",
352 aliases = ['v'],parents = [path_parser],
/linux-master/drivers/clk/ti/
H A Dclkctrl.c287 u16 offset, u8 bit, const char * const *parents,
307 init.parent_names = parents;
348 data->bit, data->parents, 1,
367 pname = data->parents;
383 data->bit, data->parents, num_parents,
419 data->bit, data->parents, 1,
285 _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider, struct device_node *node, struct clk_hw *clk_hw, u16 offset, u8 bit, const char * const *parents, int num_parents, const struct clk_ops *ops, const char *clkctrl_name) argument
/linux-master/drivers/clk/
H A Dclk.c69 struct clk_parent_map *parents; member in struct:clk_core
486 const char *name = core->parents[p_index].fw_name;
487 int index = core->parents[p_index].index;
517 struct clk_parent_map *entry = &core->parents[index];
544 if (!core || index >= core->num_parents || !core->parents)
547 if (!core->parents[index].core)
550 return core->parents[index].core;
2026 if (core->parents[i].core == parent)
2030 if (core->parents[i].core)
2034 if (core->parents[
4241 struct clk_parent_map *parents, *parent; local
5433 of_clk_parent_fill(struct device_node *np, const char **parents, unsigned int size) argument
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/linux-master/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c45 const struct clk_parent_data *parents; member in struct:mpfs_ccc_pll_hw_clock
107 .parents = _parents, \
211 pll_hw->parents,
/linux-master/drivers/clk/pxa/
H A Dclk-pxa3xx.c221 #define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \
223 PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
230 #define PXA3XX_CKEN_1RATE(dev_id, con_id, bit, parents) \
231 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
/linux-master/drivers/clk/mvebu/
H A Dkirkwood.c247 const char **parents; member in struct:clk_muxing_soc_desc
319 desc[n].parents, desc[n].num_parents,
/linux-master/drivers/clk/zynqmp/
H A Dpll.c306 * @parents: Name of this clock's parents
307 * @num_parents: Number of parents
313 const char * const *parents,
327 init.parent_names = parents;
312 zynqmp_clk_register_pll(const char *name, u32 clk_id, const char * const *parents, u8 num_parents, const struct clock_topology *nodes) argument
H A Ddivider.c19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
266 * @parents: Name of this clock's parents
267 * @num_parents: Number of parents
274 const char * const *parents,
296 init.parent_names = parents;
272 zynqmp_clk_register_divider(const char *name, u32 clk_id, const char * const *parents, u8 num_parents, const struct clock_topology *nodes) argument
/linux-master/drivers/clk/ingenic/
H A Dcgu.c347 * over any -1's in the parents array.
350 if (clk_info->parents[i] != -1)
370 * 1 for any -1 in the parents array preceding the given
372 * clk_info->parents which does not equal -1.
377 if (clk_info->parents[hw_idx] == -1)
652 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names));
706 num_possible = ARRAY_SIZE(clk_info->parents);
709 if (clk_info->parents[i] == -1)
712 parent = cgu->clocks.clks[clk_info->parents[i]];
721 BUG_ON(clk_info->parents[
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/linux-master/drivers/clk/imx/
H A Dclk-imx8mp-audiomix.c153 const struct clk_parent_data *parents; /* For mux */ member in struct:clk_imx8mp_audiomix_sel
212 sels[i].name, sels[i].parents,

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