1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (C) 2008-2009 The GameCube Linux Team
3// Copyright (C) 2008,2009 Albert Herranz
4// Copyright (C) 2017-2018 Jonathan Neusch��fer
5//
6// Nintendo Wii (Hollywood) GPIO driver
7
8#include <linux/gpio/driver.h>
9#include <linux/io.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/platform_device.h>
14#include <linux/seq_file.h>
15#include <linux/slab.h>
16
17/*
18 * Register names and offsets courtesy of WiiBrew:
19 * https://wiibrew.org/wiki/Hardware/Hollywood_GPIOs
20 *
21 * Note that for most registers, there are two versions:
22 * - HW_GPIOB_* Is always accessible by the Broadway PowerPC core, but does
23 *   always give access to all GPIO lines
24 * - HW_GPIO_* Is only accessible by the Broadway PowerPC code if the memory
25 *   firewall (AHBPROT) in the Hollywood chipset has been configured to allow
26 *   such access.
27 *
28 * The ownership of each GPIO line can be configured in the HW_GPIO_OWNER
29 * register: A one bit configures the line for access via the HW_GPIOB_*
30 * registers, a zero bit indicates access via HW_GPIO_*. This driver uses
31 * HW_GPIOB_*.
32 */
33#define HW_GPIOB_OUT		0x00
34#define HW_GPIOB_DIR		0x04
35#define HW_GPIOB_IN		0x08
36#define HW_GPIOB_INTLVL		0x0c
37#define HW_GPIOB_INTFLAG	0x10
38#define HW_GPIOB_INTMASK	0x14
39#define HW_GPIOB_INMIR		0x18
40#define HW_GPIO_ENABLE		0x1c
41#define HW_GPIO_OUT		0x20
42#define HW_GPIO_DIR		0x24
43#define HW_GPIO_IN		0x28
44#define HW_GPIO_INTLVL		0x2c
45#define HW_GPIO_INTFLAG		0x30
46#define HW_GPIO_INTMASK		0x34
47#define HW_GPIO_INMIR		0x38
48#define HW_GPIO_OWNER		0x3c
49
50struct hlwd_gpio {
51	struct gpio_chip gpioc;
52	struct device *dev;
53	void __iomem *regs;
54	int irq;
55	u32 edge_emulation;
56	u32 rising_edge, falling_edge;
57};
58
59static void hlwd_gpio_irqhandler(struct irq_desc *desc)
60{
61	struct hlwd_gpio *hlwd =
62		gpiochip_get_data(irq_desc_get_handler_data(desc));
63	struct irq_chip *chip = irq_desc_get_chip(desc);
64	unsigned long flags;
65	unsigned long pending;
66	int hwirq;
67	u32 emulated_pending;
68
69	raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
70	pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
71	pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
72
73	/* Treat interrupts due to edge trigger emulation separately */
74	emulated_pending = hlwd->edge_emulation & pending;
75	pending &= ~emulated_pending;
76	if (emulated_pending) {
77		u32 level, rising, falling;
78
79		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
80		rising = level & emulated_pending;
81		falling = ~level & emulated_pending;
82
83		/* Invert the levels */
84		iowrite32be(level ^ emulated_pending,
85			    hlwd->regs + HW_GPIOB_INTLVL);
86
87		/* Ack all emulated-edge interrupts */
88		iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
89
90		/* Signal interrupts only on the correct edge */
91		rising &= hlwd->rising_edge;
92		falling &= hlwd->falling_edge;
93
94		/* Mark emulated interrupts as pending */
95		pending |= rising | falling;
96	}
97	raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
98
99	chained_irq_enter(chip, desc);
100
101	for_each_set_bit(hwirq, &pending, 32)
102		generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
103
104	chained_irq_exit(chip, desc);
105}
106
107static void hlwd_gpio_irq_ack(struct irq_data *data)
108{
109	struct hlwd_gpio *hlwd =
110		gpiochip_get_data(irq_data_get_irq_chip_data(data));
111
112	iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
113}
114
115static void hlwd_gpio_irq_mask(struct irq_data *data)
116{
117	struct hlwd_gpio *hlwd =
118		gpiochip_get_data(irq_data_get_irq_chip_data(data));
119	unsigned long flags;
120	u32 mask;
121
122	raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
123	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
124	mask &= ~BIT(data->hwirq);
125	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
126	raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
127	gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data));
128}
129
130static void hlwd_gpio_irq_unmask(struct irq_data *data)
131{
132	struct hlwd_gpio *hlwd =
133		gpiochip_get_data(irq_data_get_irq_chip_data(data));
134	unsigned long flags;
135	u32 mask;
136
137	gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data));
138	raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
139	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
140	mask |= BIT(data->hwirq);
141	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
142	raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
143}
144
145static void hlwd_gpio_irq_enable(struct irq_data *data)
146{
147	hlwd_gpio_irq_ack(data);
148	hlwd_gpio_irq_unmask(data);
149}
150
151static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
152					  unsigned int flow_type)
153{
154	u32 level, state;
155
156	/* Set the trigger level to the inactive level */
157	level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
158	state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
159	level &= ~BIT(hwirq);
160	level |= state ^ BIT(hwirq);
161	iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
162
163	hlwd->edge_emulation |= BIT(hwirq);
164	hlwd->rising_edge &= ~BIT(hwirq);
165	hlwd->falling_edge &= ~BIT(hwirq);
166	if (flow_type & IRQ_TYPE_EDGE_RISING)
167		hlwd->rising_edge |= BIT(hwirq);
168	if (flow_type & IRQ_TYPE_EDGE_FALLING)
169		hlwd->falling_edge |= BIT(hwirq);
170}
171
172static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
173{
174	struct hlwd_gpio *hlwd =
175		gpiochip_get_data(irq_data_get_irq_chip_data(data));
176	unsigned long flags;
177	u32 level;
178
179	raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
180
181	hlwd->edge_emulation &= ~BIT(data->hwirq);
182
183	switch (flow_type) {
184	case IRQ_TYPE_LEVEL_HIGH:
185		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
186		level |= BIT(data->hwirq);
187		iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
188		break;
189	case IRQ_TYPE_LEVEL_LOW:
190		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
191		level &= ~BIT(data->hwirq);
192		iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
193		break;
194	case IRQ_TYPE_EDGE_RISING:
195	case IRQ_TYPE_EDGE_FALLING:
196	case IRQ_TYPE_EDGE_BOTH:
197		hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
198		break;
199	default:
200		raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
201		return -EINVAL;
202	}
203
204	raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
205	return 0;
206}
207
208static void hlwd_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
209{
210	struct hlwd_gpio *hlwd =
211		gpiochip_get_data(irq_data_get_irq_chip_data(data));
212
213	seq_printf(p, dev_name(hlwd->dev));
214}
215
216static const struct irq_chip hlwd_gpio_irq_chip = {
217	.irq_mask = hlwd_gpio_irq_mask,
218	.irq_unmask = hlwd_gpio_irq_unmask,
219	.irq_enable = hlwd_gpio_irq_enable,
220	.irq_set_type = hlwd_gpio_irq_set_type,
221	.irq_print_chip = hlwd_gpio_irq_print_chip,
222	.flags = IRQCHIP_IMMUTABLE,
223	GPIOCHIP_IRQ_RESOURCE_HELPERS,
224};
225
226static int hlwd_gpio_probe(struct platform_device *pdev)
227{
228	struct hlwd_gpio *hlwd;
229	u32 ngpios;
230	int res;
231
232	hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);
233	if (!hlwd)
234		return -ENOMEM;
235
236	hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
237	if (IS_ERR(hlwd->regs))
238		return PTR_ERR(hlwd->regs);
239
240	hlwd->dev = &pdev->dev;
241
242	/*
243	 * Claim all GPIOs using the OWNER register. This will not work on
244	 * systems where the AHBPROT memory firewall hasn't been configured to
245	 * permit PPC access to HW_GPIO_*.
246	 *
247	 * Note that this has to happen before bgpio_init reads the
248	 * HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong
249	 * values.
250	 */
251	iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
252
253	res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
254			hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
255			NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
256			BGPIOF_BIG_ENDIAN_BYTE_ORDER);
257	if (res < 0) {
258		dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res);
259		return res;
260	}
261
262	res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios);
263	if (res)
264		ngpios = 32;
265	hlwd->gpioc.ngpio = ngpios;
266
267	/* Mask and ack all interrupts */
268	iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
269	iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
270
271	/*
272	 * If this GPIO controller is not marked as an interrupt controller in
273	 * the DT, skip interrupt support.
274	 */
275	if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
276		struct gpio_irq_chip *girq;
277
278		hlwd->irq = platform_get_irq(pdev, 0);
279		if (hlwd->irq < 0) {
280			dev_info(&pdev->dev, "platform_get_irq returned %d\n",
281				 hlwd->irq);
282			return hlwd->irq;
283		}
284
285		girq = &hlwd->gpioc.irq;
286		gpio_irq_chip_set_chip(girq, &hlwd_gpio_irq_chip);
287		girq->parent_handler = hlwd_gpio_irqhandler;
288		girq->num_parents = 1;
289		girq->parents = devm_kcalloc(&pdev->dev, 1,
290					     sizeof(*girq->parents),
291					     GFP_KERNEL);
292		if (!girq->parents)
293			return -ENOMEM;
294		girq->parents[0] = hlwd->irq;
295		girq->default_type = IRQ_TYPE_NONE;
296		girq->handler = handle_level_irq;
297	}
298
299	return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
300}
301
302static const struct of_device_id hlwd_gpio_match[] = {
303	{ .compatible = "nintendo,hollywood-gpio", },
304	{},
305};
306MODULE_DEVICE_TABLE(of, hlwd_gpio_match);
307
308static struct platform_driver hlwd_gpio_driver = {
309	.driver	= {
310		.name		= "gpio-hlwd",
311		.of_match_table	= hlwd_gpio_match,
312	},
313	.probe	= hlwd_gpio_probe,
314};
315module_platform_driver(hlwd_gpio_driver);
316
317MODULE_AUTHOR("Jonathan Neusch��fer <j.neuschaefer@gmx.net>");
318MODULE_DESCRIPTION("Nintendo Wii GPIO driver");
319MODULE_LICENSE("GPL");
320