Searched refs:cycle (Results 51 - 75 of 91) sorted by relevance

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/linux-master/drivers/usb/early/
H A Dxhci-dbc.c469 u32 cycle; local
488 cycle = ring->cycle_state;
492 if (cycle)
511 * the cycle bit:
514 if (cycle)
515 trb->field[3] |= cpu_to_le32(cycle);
807 * Add a barrier between reading the cycle flag and any
/linux-master/arch/powerpc/kernel/
H A Dsysfs.c244 u64 cycle; local
247 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
249 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
251 if (!cycle)
254 return ilog2(cycle);
/linux-master/drivers/media/rc/
H A Dserial_ir.c478 static int serial_ir_tx_duty_cycle(struct rc_dev *dev, u32 cycle);
670 static int serial_ir_tx_duty_cycle(struct rc_dev *dev, u32 cycle) argument
672 serial_ir.duty_cycle = cycle;
/linux-master/arch/alpha/lib/
H A Dev6-memset.S153 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
173 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
331 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
351 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
519 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
539 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
H A Dev6-stxcpy.S81 cmpbge zero, t1, t8 # E : (3 cycle stall)
253 zap t0, t8, t0 # U : kill dest bytes <= null (2 cycle data stall)
H A Dev6-copy_user.S56 beq $3, $destaligned # .. U .. .. : 2nd (one cycle fetcher stall)
59 * The fetcher stall also hides the 1 cycle cross-cluster stall for $3 (L --> U)
H A Dev6-clear_user.S120 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
158 cmovlt $5, $16, $3 # E : U L L U : Latency 2, extra mapping cycle
H A Dev6-stxncpy.S200 extqh t2, a1, t4 # U : (3 cycle stall on t2)
260 extqh t2, a1, t0 # U : extract low bits (2 cycle stall)
/linux-master/drivers/scsi/
H A Desp_scsi.h249 #define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
/linux-master/include/linux/
H A Dfirewire.h500 u32 cycle, size_t header_length,
532 int cycle, int sync, int tags);
/linux-master/arch/arc/lib/
H A Dmemcmp.S57 ; one more load latency cycle
/linux-master/drivers/firewire/
H A Dcore.h100 s32 cycle, u32 sync, u32 tags);
/linux-master/fs/xfs/
H A Dxfs_log_recover.c264 * log which contains the given cycle. It uses a binary search algorithm.
274 uint cycle)
289 if (mid_cycle == cycle)
320 uint cycle; local
351 cycle = xlog_get_cycle(buf);
352 if (cycle == stop_on_cycle_no) {
468 * last_blk will be the 1st block # with a given cycle #. We may end
488 * LR have complete transactions. We only know that a cycle number of
489 * current cycle number -1 won't be present in the log if we start writing
493 * cycle numbe
269 xlog_find_cycle_start( struct xlog *log, char *buffer, xfs_daddr_t first_blk, xfs_daddr_t *last_blk, uint cycle) argument
1486 xlog_add_record( struct xlog *log, char *buf, int cycle, int block, int tail_cycle, int tail_block) argument
1508 xlog_write_log_records( struct xlog *log, int cycle, int start_block, int blocks, int tail_cycle, int tail_block) argument
[all...]
/linux-master/drivers/net/wireless/realtek/rtw89/
H A Dcoex.c7385 /* cycle statistics exceptions */
7465 u16 cycle, c_begin, c_end, store_index; local
7473 " %-15s : cycle:%d, bcn[all:%d/all_ok:%d/bt:%d/bt_ok:%d]",
7522 /* 1 cycle record 1 wl-slot and 1 bt-slot */
7532 for (cycle = c_begin; cycle <= c_end; cycle++) {
7534 store_index = ((cycle - 1) % slot_pair) * 2;
7565 ", cycle[PSTDMA:%d/TDMA:%d], ",
7593 u16 cycle, c_begi local
7723 u16 cycle, c_begin, c_end, store_index; local
7855 u16 cycle, c_begin, c_end, store_index; local
[all...]
/linux-master/arch/sh/lib/
H A Dmemcpy-sh4.S175 mov r6, r0 ! 5 MT (0 cycle latency)
184 mov r4, r0 ! 5 MT (0 cycle latency)
197 ! cycle counts for differnet sizes using byte-at-a-time vs. optimised):
/linux-master/fs/xfs/libxfs/
H A Dxfs_log_format.h26 #define XLOG_HEADER_MAGIC_NUM 0xFEEDbabe /* Invalid cycle number */
33 #define XLOG_HEADER_CYCLE_SIZE (32*1024) /* cycle data in header */
57 static inline xfs_lsn_t xlog_assign_lsn(uint cycle, uint block) argument
59 return ((xfs_lsn_t)cycle << 32) | block;
165 __be32 h_cycle; /* write cycle of log : 4 */
181 __be32 xh_cycle; /* write cycle of log : 4 */
/linux-master/drivers/usb/host/
H A Dxhci-dbgcap.c268 u32 length, control, cycle; local
277 cycle = ring->cycle_state;
281 if (cycle)
295 * the cycle bit:
299 if (cycle)
864 * Add a barrier between reading the cycle flag and any
/linux-master/drivers/greybus/
H A Doperation.c727 unsigned int cycle; local
750 cycle = (unsigned int)atomic_inc_return(&connection->op_cycle);
751 operation->id = (u16)(cycle % U16_MAX + 1);
/linux-master/drivers/clocksource/
H A Darm_arch_timer.c1809 int kvm_arch_ptp_get_crosststamp(u64 *cycle, struct timespec64 *ts, argument
1832 if (cycle)
1833 *cycle = (u64)hvc_res.a2 << 32 | hvc_res.a3;
/linux-master/drivers/media/firewire/
H A Dfiredtv-fw.c98 static void handle_iso(struct fw_iso_context *context, u32 cycle, argument
/linux-master/drivers/net/ethernet/freescale/enetc/
H A Denetc_qos.c724 static int get_start_ns(u64 now, u64 cycle, u64 *start) argument
728 if (!cycle)
731 n = div64_u64(now, cycle);
733 *start = (n + 1) * cycle;
/linux-master/drivers/perf/hisilicon/
H A Dhisi_uncore_pa_pmu.c324 HISI_PMU_EVENT_ATTR(cycle, 0x78),
/linux-master/drivers/ata/
H A Dpata_octeon_cf.c160 pause = (int)timing.cycle - (int)timing.active -
188 /* Time to wait to complete the cycle. */
228 T0 = timing->cycle;
H A Dpata_ep93xx.c269 unsigned long t0 = reg ? t->cyc8b : t->cycle;
303 unsigned long t0 = reg ? t->cyc8b : t->cycle;
/linux-master/sound/sparc/
H A Ddbri.c894 int length, int cycle)
923 * "If transmission on edges 0 or 1 is desired, then cycle n
927 if (prevpipe == 16 && cycle == 0)
928 cycle = dbri->chi_bpf;
934 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
939 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
1517 * offset by eight bits, so we add eight to all the "cycle"
892 link_time_slot(struct snd_dbri *dbri, int pipe, int prevpipe, int nextpipe, int length, int cycle) argument

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