1185380Ssam/* SPDX-License-Identifier: GPL-2.0 */ 2187831Ssam/* esp_scsi.h: Defines and structures for the ESP driver. 3185380Ssam * 4185380Ssam * Copyright (C) 2007 David S. Miller (davem@davemloft.net) 5185380Ssam */ 6185380Ssam 7185380Ssam#ifndef _ESP_SCSI_H 8185380Ssam#define _ESP_SCSI_H 9185380Ssam 10185380Ssam /* Access Description Offset */ 11185380Ssam#define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */ 12185380Ssam#define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */ 13185380Ssam#define ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */ 14185380Ssam#define ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */ 15185380Ssam#define ESP_STATUS 0x04UL /* ro ESP status register 0x10 */ 16185380Ssam#define ESP_BUSID ESP_STATUS /* wo BusID for sel/resel 0x10 */ 17187831Ssam#define ESP_INTRPT 0x05UL /* ro Kind of interrupt 0x14 */ 18185380Ssam#define ESP_TIMEO ESP_INTRPT /* wo Timeout for sel/resel 0x14 */ 19185380Ssam#define ESP_SSTEP 0x06UL /* ro Sequence step register 0x18 */ 20185380Ssam#define ESP_STP ESP_SSTEP /* wo Transfer period/sync 0x18 */ 21185380Ssam#define ESP_FFLAGS 0x07UL /* ro Bits current FIFO info 0x1c */ 22185380Ssam#define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */ 23185380Ssam#define ESP_CFG1 0x08UL /* rw First cfg register 0x20 */ 24185380Ssam#define ESP_CFACT 0x09UL /* wo Clock conv factor 0x24 */ 25185380Ssam#define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */ 26185380Ssam#define ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */ 27185380Ssam#define ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */ 28185380Ssam#define ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */ 29185380Ssam#define ESP_CFG4 0x0dUL /* rw Fourth cfg register 0x34 */ 30185380Ssam#define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */ 31185380Ssam#define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */ 32185380Ssam#define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */ 33185380Ssam#define ESP_FGRND 0x0fUL /* rw Data base for fifo 0x3c */ 34185380Ssam#define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */ 35185380Ssam 36185380Ssam#define SBUS_ESP_REG_SIZE 0x40UL 37185380Ssam 38185380Ssam/* Bitfield meanings for the above registers. */ 39185380Ssam 40185380Ssam/* ESP config reg 1, read-write, found on all ESP chips */ 41185380Ssam#define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */ 42185380Ssam#define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */ 43185380Ssam#define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */ 44185380Ssam#define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */ 45185380Ssam#define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */ 46185380Ssam#define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */ 47185380Ssam 48185380Ssam/* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */ 49185380Ssam#define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */ 50185380Ssam#define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */ 51185380Ssam#define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */ 52185380Ssam#define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */ 53185380Ssam#define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */ 54185380Ssam#define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */ 55185380Ssam#define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */ 56185380Ssam#define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */ 57185380Ssam#define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,216) */ 58185380Ssam#define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */ 59185380Ssam#define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */ 60185380Ssam#define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */ 61185380Ssam#define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */ 62185380Ssam 63185380Ssam/* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */ 64185380Ssam#define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */ 65185380Ssam#define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */ 66185380Ssam#define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */ 67185380Ssam#define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */ 68185380Ssam#define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */ 69185380Ssam#define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */ 70185380Ssam#define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */ 71185380Ssam#define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */ 72185380Ssam#define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */ 73185380Ssam#define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */ 74185380Ssam#define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */ 75185380Ssam#define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */ 76185380Ssam#define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */ 77185380Ssam#define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */ 78185380Ssam#define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */ 79185380Ssam#define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */ 80185380Ssam 81185380Ssam/* ESP config register 4 read-write */ 82185380Ssam#define ESP_CONFIG4_BBTE 0x01 /* Back-to-back transfers (fsc) */ 83185380Ssam#define ESP_CONGIG4_TEST 0x02 /* Transfer counter test mode (fsc) */ 84185380Ssam#define ESP_CONFIG4_RADE 0x04 /* Active negation (am53c974/fsc) */ 85185380Ssam#define ESP_CONFIG4_RAE 0x08 /* Act. negation REQ/ACK (am53c974) */ 86185380Ssam#define ESP_CONFIG4_PWD 0x20 /* Reduced power feature (am53c974) */ 87185380Ssam#define ESP_CONFIG4_GE0 0x40 /* Glitch eater bit 0 (am53c974) */ 88185380Ssam#define ESP_CONFIG4_GE1 0x80 /* Glitch eater bit 1 (am53c974) */ 89185380Ssam 90185380Ssam#define ESP_CONFIG_GE_12NS (0) 91185380Ssam#define ESP_CONFIG_GE_25NS (ESP_CONFIG_GE1) 92185380Ssam#define ESP_CONFIG_GE_35NS (ESP_CONFIG_GE0) 93185380Ssam#define ESP_CONFIG_GE_0NS (ESP_CONFIG_GE0 | ESP_CONFIG_GE1) 94185380Ssam 95185380Ssam/* ESP command register read-write */ 96185380Ssam/* Group 1 commands: These may be sent at any point in time to the ESP 97185380Ssam * chip. None of them can generate interrupts 'cept 98185380Ssam * the "SCSI bus reset" command if you have not disabled 99185380Ssam * SCSI reset interrupts in the config1 ESP register. 100185380Ssam */ 101185380Ssam#define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */ 102185380Ssam#define ESP_CMD_FLUSH 0x01 /* FIFO Flush */ 103185380Ssam#define ESP_CMD_RC 0x02 /* Chip reset */ 104185380Ssam#define ESP_CMD_RS 0x03 /* SCSI bus reset */ 105185380Ssam 106185380Ssam/* Group 2 commands: ESP must be an initiator and connected to a target 107185380Ssam * for these commands to work. 108185380Ssam */ 109185380Ssam#define ESP_CMD_TI 0x10 /* Transfer Information */ 110185380Ssam#define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */ 111185380Ssam#define ESP_CMD_MOK 0x12 /* Message okie-dokie */ 112185380Ssam#define ESP_CMD_TPAD 0x18 /* Transfer Pad */ 113185380Ssam#define ESP_CMD_SATN 0x1a /* Set ATN */ 114185380Ssam#define ESP_CMD_RATN 0x1b /* De-assert ATN */ 115185380Ssam 116185380Ssam/* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected 117185380Ssam * to a target as the initiator for these commands to work. 118185380Ssam */ 119185380Ssam#define ESP_CMD_SMSG 0x20 /* Send message */ 120185380Ssam#define ESP_CMD_SSTAT 0x21 /* Send status */ 121185380Ssam#define ESP_CMD_SDATA 0x22 /* Send data */ 122185380Ssam#define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */ 123185380Ssam#define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */ 124185380Ssam#define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */ 125185380Ssam#define ESP_CMD_DCNCT 0x27 /* Disconnect */ 126185380Ssam#define ESP_CMD_RMSG 0x28 /* Receive Message */ 127185380Ssam#define ESP_CMD_RCMD 0x29 /* Receive Command */ 128185380Ssam#define ESP_CMD_RDATA 0x2a /* Receive Data */ 129185380Ssam#define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */ 130185380Ssam 131185380Ssam/* Group 4 commands: The ESP must be in the disconnected state and must 132185380Ssam * not be connected to any targets as initiator for 133185380Ssam * these commands to work. 134185380Ssam */ 135185380Ssam#define ESP_CMD_RSEL 0x40 /* Reselect */ 136185380Ssam#define ESP_CMD_SEL 0x41 /* Select w/o ATN */ 137185380Ssam#define ESP_CMD_SELA 0x42 /* Select w/ATN */ 138185380Ssam#define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */ 139185380Ssam#define ESP_CMD_ESEL 0x44 /* Enable selection */ 140185380Ssam#define ESP_CMD_DSEL 0x45 /* Disable selections */ 141185380Ssam#define ESP_CMD_SA3 0x46 /* Select w/ATN3 */ 142185380Ssam#define ESP_CMD_RSEL3 0x47 /* Reselect3 */ 143185380Ssam 144185380Ssam/* This bit enables the ESP's DMA on the SBus */ 145185380Ssam#define ESP_CMD_DMA 0x80 /* Do DMA? */ 146185380Ssam 147185380Ssam/* ESP status register read-only */ 148185380Ssam#define ESP_STAT_PIO 0x01 /* IO phase bit */ 149185380Ssam#define ESP_STAT_PCD 0x02 /* CD phase bit */ 150185380Ssam#define ESP_STAT_PMSG 0x04 /* MSG phase bit */ 151185380Ssam#define ESP_STAT_PMASK 0x07 /* Mask of phase bits */ 152185380Ssam#define ESP_STAT_TDONE 0x08 /* Transfer Completed */ 153185380Ssam#define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */ 154185380Ssam#define ESP_STAT_PERR 0x20 /* Parity error */ 155185380Ssam#define ESP_STAT_SPAM 0x40 /* Real bad error */ 156185380Ssam/* This indicates the 'interrupt pending' condition on esp236, it is a reserved 157185380Ssam * bit on other revs of the ESP. 158185380Ssam */ 159224514Sadrian#define ESP_STAT_INTR 0x80 /* Interrupt */ 160224514Sadrian 161185380Ssam/* The status register can be masked with ESP_STAT_PMASK and compared 162185380Ssam * with the following values to determine the current phase the ESP 163185380Ssam * (at least thinks it) is in. For our purposes we also add our own 164185380Ssam * software 'done' bit for our phase management engine. 165185380Ssam */ 166185380Ssam#define ESP_DOP (0) /* Data Out */ 167185380Ssam#define ESP_DIP (ESP_STAT_PIO) /* Data In */ 168185380Ssam#define ESP_CMDP (ESP_STAT_PCD) /* Command */ 169185380Ssam#define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */ 170185380Ssam#define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */ 171185380Ssam#define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */ 172185380Ssam 173185380Ssam/* HME only: status 2 register */ 174185380Ssam#define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */ 175185380Ssam#define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */ 176185380Ssam#define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */ 177185380Ssam#define ESP_STAT2_CREGA 0x08 /* The command reg is active now */ 178224514Sadrian#define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */ 179185380Ssam#define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */ 180224514Sadrian#define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */ 181224514Sadrian#define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */ 182224514Sadrian 183224514Sadrian/* ESP interrupt register read-only */ 184224514Sadrian#define ESP_INTR_S 0x01 /* Select w/o ATN */ 185224514Sadrian#define ESP_INTR_SATN 0x02 /* Select w/ATN */ 186224514Sadrian#define ESP_INTR_RSEL 0x04 /* Reselected */ 187224514Sadrian#define ESP_INTR_FDONE 0x08 /* Function done */ 188224514Sadrian#define ESP_INTR_BSERV 0x10 /* Bus service */ 189224514Sadrian#define ESP_INTR_DC 0x20 /* Disconnect */ 190224514Sadrian#define ESP_INTR_IC 0x40 /* Illegal command given */ 191224514Sadrian#define ESP_INTR_SR 0x80 /* SCSI bus reset detected */ 192224514Sadrian 193224514Sadrian/* ESP sequence step register read-only */ 194224514Sadrian#define ESP_STEP_VBITS 0x07 /* Valid bits */ 195224514Sadrian#define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */ 196224514Sadrian#define ESP_STEP_SID 0x01 /* One msg byte sent */ 197224514Sadrian#define ESP_STEP_NCMD 0x02 /* Was not in command phase */ 198224514Sadrian#define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd 199224514Sadrian * bytes to be lost 200224514Sadrian */ 201224514Sadrian#define ESP_STEP_FINI4 0x04 /* Command was sent ok */ 202224514Sadrian 203224514Sadrian/* Ho hum, some ESP's set the step register to this as well... */ 204224514Sadrian#define ESP_STEP_FINI5 0x05 205224514Sadrian#define ESP_STEP_FINI6 0x06 206224514Sadrian#define ESP_STEP_FINI7 0x07 207224514Sadrian 208224514Sadrian/* ESP chip-test register read-write */ 209224514Sadrian#define ESP_TEST_TARG 0x01 /* Target test mode */ 210224514Sadrian#define ESP_TEST_INI 0x02 /* Initiator test mode */ 211224514Sadrian#define ESP_TEST_TS 0x04 /* Tristate test mode */ 212224514Sadrian 213224514Sadrian/* ESP unique ID register read-only, found on fas236+fas100a only */ 214224514Sadrian#define ESP_UID_FAM 0xf8 /* ESP family bitmask */ 215224514Sadrian 216222276Sadrian#define ESP_FAMILY(uid) (((uid) & ESP_UID_FAM) >> 3) 217222276Sadrian 218222276Sadrian/* Values for the ESP family bits */ 219222276Sadrian#define ESP_UID_F100A 0x00 /* ESP FAS100A */ 220222276Sadrian#define ESP_UID_F236 0x02 /* ESP FAS236 */ 221222276Sadrian#define ESP_UID_HME 0x0a /* FAS HME */ 222222276Sadrian#define ESP_UID_FSC 0x14 /* NCR/Symbios Logic 53CF9x-2 */ 223222276Sadrian 224185380Ssam/* ESP fifo flags register read-only */ 225222276Sadrian/* Note that the following implies a 16 byte FIFO on the ESP. */ 226185380Ssam#define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */ 227185380Ssam#define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */ 228185380Ssam#define ESP_FF_SSTEP 0xe0 /* Sequence step */ 229217684Sadrian 230227376Sadrian/* ESP clock conversion factor register write-only */ 231217925Sadrian#define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */ 232203159Srpaulo#define ESP_CCF_NEVER 0x01 /* Set it to this and die */ 233185380Ssam#define ESP_CCF_F2 0x02 /* 10MHz */ 234185380Ssam#define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */ 235185380Ssam#define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */ 236185380Ssam#define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */ 237185380Ssam#define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */ 238185380Ssam#define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */ 239185380Ssam 240185380Ssam/* HME only... */ 241185380Ssam#define ESP_BUSID_RESELID 0x10 242185380Ssam#define ESP_BUSID_CTR32BIT 0x40 243185380Ssam 244185380Ssam#define ESP_BUS_TIMEOUT 250 /* In milli-seconds */ 245185380Ssam#define ESP_TIMEO_CONST 8192 246185380Ssam#define ESP_NEG_DEFP(mhz, cfact) \ 247185380Ssam ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact))) 248185380Ssam#define ESP_HZ_TO_CYCLE(hertz) ((1000000000) / ((hertz) / 1000)) 249185380Ssam#define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000)) 250185380Ssam 251185380Ssam/* For slow to medium speed input clock rates we shoot for 5mb/s, but for high 252185380Ssam * input clock rates we try to do 10mb/s although I don't think a transfer can 253185380Ssam * even run that fast with an ESP even with DMA2 scatter gather pipelining. 254185380Ssam */ 255185380Ssam#define SYNC_DEFP_SLOW 0x32 /* 5mb/s */ 256185380Ssam#define SYNC_DEFP_FAST 0x19 /* 10mb/s */ 257185380Ssam 258185380Ssamstruct esp_cmd_priv { 259185380Ssam int num_sg; 260185380Ssam int cur_residue; 261185380Ssam struct scatterlist *prv_sg; 262217684Sadrian struct scatterlist *cur_sg; 263185380Ssam int tot_residue; 264185380Ssam}; 265185380Ssam 266185380Ssam#define ESP_CMD_PRIV(cmd) ((struct esp_cmd_priv *)scsi_cmd_priv(cmd)) 267185380Ssam 268185380Ssam/* NOTE: this enum is ordered based on chip features! */ 269185380Ssamenum esp_rev { 270185380Ssam ESP100, /* NCR53C90 - very broken */ 271185380Ssam ESP100A, /* NCR53C90A */ 272185380Ssam ESP236, 273185380Ssam FAS236, 274185380Ssam PCSCSI, /* AM53c974 */ 275185380Ssam FSC, /* NCR/Symbios Logic 53CF9x-2 */ 276185380Ssam FAS100A, 277185380Ssam FAST, 278185380Ssam FASHME, 279185380Ssam}; 280185380Ssam 281185380Ssamstruct esp_cmd_entry { 282185380Ssam struct list_head list; 283185380Ssam 284185380Ssam struct scsi_cmnd *cmd; 285185380Ssam 286185380Ssam unsigned int saved_cur_residue; 287185380Ssam struct scatterlist *saved_prv_sg; 288185380Ssam struct scatterlist *saved_cur_sg; 289185380Ssam unsigned int saved_tot_residue; 290185380Ssam 291185380Ssam u8 flags; 292185380Ssam#define ESP_CMD_FLAG_WRITE 0x01 /* DMA is a write */ 293185380Ssam#define ESP_CMD_FLAG_AUTOSENSE 0x04 /* Doing automatic REQUEST_SENSE */ 294185380Ssam#define ESP_CMD_FLAG_RESIDUAL 0x08 /* AM53c974 BLAST residual */ 295185380Ssam 296185380Ssam u8 tag[2]; 297185380Ssam u8 orig_tag[2]; 298185380Ssam 299185380Ssam u8 status; 300185380Ssam u8 message; 301185380Ssam 302185380Ssam unsigned char *sense_ptr; 303217684Sadrian unsigned char *saved_sense_ptr; 304185380Ssam dma_addr_t sense_dma; 305185380Ssam 306185380Ssam struct completion *eh_done; 307185380Ssam}; 308185380Ssam 309185380Ssam#define ESP_DEFAULT_TAGS 16 310185380Ssam 311185380Ssam#define ESP_MAX_TARGET 16 312185380Ssam#define ESP_MAX_LUN 8 313185380Ssam#define ESP_MAX_TAG 256 314185380Ssam 315185380Ssamstruct esp_lun_data { 316217684Sadrian struct esp_cmd_entry *non_tagged_cmd; 317227376Sadrian int num_tagged; 318217925Sadrian int hold; 319203159Srpaulo struct esp_cmd_entry *tagged_cmds[ESP_MAX_TAG]; 320185380Ssam}; 321185380Ssam 322185380Ssamstruct esp_target_data { 323185380Ssam /* These are the ESP_STP, ESP_SOFF, and ESP_CFG3 register values which 324185380Ssam * match the currently negotiated settings for this target. The SCSI 325185380Ssam * protocol values are maintained in spi_{offset,period,wide}(starget). 326185380Ssam */ 327185380Ssam u8 esp_period; 328185380Ssam u8 esp_offset; 329185380Ssam u8 esp_config3; 330185380Ssam 331185380Ssam u8 flags; 332185380Ssam#define ESP_TGT_WIDE 0x01 333185380Ssam#define ESP_TGT_DISCONNECT 0x02 334185380Ssam#define ESP_TGT_NEGO_WIDE 0x04 335217684Sadrian#define ESP_TGT_NEGO_SYNC 0x08 336227376Sadrian#define ESP_TGT_CHECK_NEGO 0x40 337217925Sadrian#define ESP_TGT_BROKEN 0x80 338203159Srpaulo 339185380Ssam /* When ESP_TGT_CHECK_NEGO is set, on the next scsi command to this 340185380Ssam * device we will try to negotiate the following parameters. 341185380Ssam */ 342185380Ssam u8 nego_goal_period; 343185380Ssam u8 nego_goal_offset; 344221600Sadrian u8 nego_goal_width; 345185380Ssam u8 nego_goal_tags; 346185380Ssam 347185380Ssam struct scsi_target *starget; 348185380Ssam}; 349185380Ssam 350185380Ssamstruct esp_event_ent { 351185380Ssam u8 type; 352185380Ssam#define ESP_EVENT_TYPE_EVENT 0x01 353185380Ssam#define ESP_EVENT_TYPE_CMD 0x02 354185380Ssam u8 val; 355185380Ssam 356185380Ssam u8 sreg; 357185380Ssam u8 seqreg; 358185380Ssam u8 sreg2; 359217925Sadrian u8 ireg; 360185380Ssam u8 select_state; 361185380Ssam u8 event; 362185380Ssam u8 __pad; 363185380Ssam}; 364185380Ssam 365185380Ssamstruct esp; 366185380Ssamstruct esp_driver_ops { 367185380Ssam /* Read and write the ESP 8-bit registers. On some 368185380Ssam * applications of the ESP chip the registers are at 4-byte 369185380Ssam * instead of 1-byte intervals. 370187831Ssam */ 371185380Ssam void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg); 372185380Ssam u8 (*esp_read8)(struct esp *esp, unsigned long reg); 373185380Ssam 374185380Ssam /* Return non-zero if there is an IRQ pending. Usually this 375185380Ssam * status bit lives in the DMA controller sitting in front of 376185380Ssam * the ESP. This has to be accurate or else the ESP interrupt 377185380Ssam * handler will not run. 378185380Ssam */ 379185380Ssam int (*irq_pending)(struct esp *esp); 380185380Ssam 381185380Ssam /* Return the maximum allowable size of a DMA transfer for a 382227377Sadrian * given buffer. 383227377Sadrian */ 384227377Sadrian u32 (*dma_length_limit)(struct esp *esp, u32 dma_addr, 385227377Sadrian u32 dma_len); 386185380Ssam 387185380Ssam /* Reset the DMA engine entirely. On return, ESP interrupts 388227377Sadrian * should be enabled. Often the interrupt enabling is 389227377Sadrian * controlled in the DMA engine. 390227377Sadrian */ 391227377Sadrian void (*reset_dma)(struct esp *esp); 392185380Ssam 393185380Ssam /* Drain any pending DMA in the DMA engine after a transfer. 394227378Sadrian * This is for writes to memory. 395227378Sadrian */ 396227378Sadrian void (*dma_drain)(struct esp *esp); 397227378Sadrian 398227378Sadrian /* Invalidate the DMA engine after a DMA transfer. */ 399227378Sadrian void (*dma_invalidate)(struct esp *esp); 400227378Sadrian 401227378Sadrian /* Setup an ESP command that will use a DMA transfer. 402227378Sadrian * The 'esp_count' specifies what transfer length should be 403227378Sadrian * programmed into the ESP transfer counter registers, whereas 404227378Sadrian * the 'dma_count' is the length that should be programmed into 405227378Sadrian * the DMA controller. Usually they are the same. If 'write' 406185380Ssam * is non-zero, this transfer is a write into memory. 'cmd' 407185380Ssam * holds the ESP command that should be issued by calling 408185380Ssam * scsi_esp_cmd() at the appropriate time while programming 409185380Ssam * the DMA hardware. 410185380Ssam */ 411185380Ssam void (*send_dma_cmd)(struct esp *esp, u32 dma_addr, u32 esp_count, 412185380Ssam u32 dma_count, int write, u8 cmd); 413185380Ssam 414185380Ssam /* Return non-zero if the DMA engine is reporting an error 415185380Ssam * currently. 416185380Ssam */ 417185380Ssam int (*dma_error)(struct esp *esp); 418185380Ssam}; 419185380Ssam 420185380Ssam#define ESP_MAX_MSG_SZ 8 421185380Ssam#define ESP_EVENT_LOG_SZ 32 422185380Ssam 423185380Ssam#define ESP_QUICKIRQ_LIMIT 100 424185380Ssam#define ESP_RESELECT_TAG_LIMIT 2500 425239753Sadrian 426227376Sadrianstruct esp { 427227376Sadrian void __iomem *regs; 428227376Sadrian void __iomem *dma_regs; 429185380Ssam 430185380Ssam const struct esp_driver_ops *ops; 431185380Ssam 432185380Ssam struct Scsi_Host *host; 433185380Ssam struct device *dev; 434185380Ssam 435185380Ssam struct esp_cmd_entry *active_cmd; 436185380Ssam 437185380Ssam struct list_head queued_cmds; 438185380Ssam struct list_head active_cmds; 439239753Sadrian 440227376Sadrian u8 *command_block; 441227376Sadrian dma_addr_t command_block_dma; 442227376Sadrian 443185380Ssam unsigned int data_dma_len; 444185380Ssam 445185380Ssam /* The following are used to determine the cause of an IRQ. Upon every 446185380Ssam * IRQ entry we synchronize these with the hardware registers. 447185380Ssam */ 448185380Ssam u8 sreg; 449187831Ssam u8 seqreg; 450185380Ssam u8 sreg2; 451185380Ssam u8 ireg; 452185380Ssam 453185380Ssam u32 prev_hme_dmacsr; 454185380Ssam u8 prev_soff; 455227376Sadrian u8 prev_stp; 456227376Sadrian u8 prev_cfg3; 457227376Sadrian u8 num_tags; 458185380Ssam 459185380Ssam struct list_head esp_cmd_pool; 460185380Ssam 461185380Ssam struct esp_target_data target[ESP_MAX_TARGET]; 462185380Ssam 463185380Ssam int fifo_cnt; 464185380Ssam u8 fifo[16]; 465185380Ssam 466185380Ssam struct esp_event_ent esp_event_log[ESP_EVENT_LOG_SZ]; 467187831Ssam int esp_event_cur; 468185380Ssam 469185380Ssam u8 msg_out[ESP_MAX_MSG_SZ]; 470185380Ssam int msg_out_len; 471185380Ssam 472185380Ssam u8 msg_in[ESP_MAX_MSG_SZ]; 473185380Ssam int msg_in_len; 474185380Ssam 475185380Ssam u8 bursts; 476185380Ssam u8 config1; 477185380Ssam u8 config2; 478185380Ssam u8 config4; 479222276Sadrian 480222276Sadrian u8 scsi_id; 481185380Ssam u32 scsi_id_mask; 482185380Ssam 483185380Ssam enum esp_rev rev; 484185380Ssam 485185380Ssam u32 flags; 486185380Ssam#define ESP_FLAG_DIFFERENTIAL 0x00000001 487185380Ssam#define ESP_FLAG_RESETTING 0x00000002 488185380Ssam#define ESP_FLAG_WIDE_CAPABLE 0x00000008 489185380Ssam#define ESP_FLAG_QUICKIRQ_CHECK 0x00000010 490185380Ssam#define ESP_FLAG_DISABLE_SYNC 0x00000020 491185380Ssam#define ESP_FLAG_USE_FIFO 0x00000040 492185380Ssam#define ESP_FLAG_NO_DMA_MAP 0x00000080 493239753Sadrian 494185380Ssam u8 select_state; 495185380Ssam#define ESP_SELECT_NONE 0x00 /* Not selecting */ 496185380Ssam#define ESP_SELECT_BASIC 0x01 /* Select w/o MSGOUT phase */ 497185380Ssam#define ESP_SELECT_MSGOUT 0x02 /* Select with MSGOUT */ 498185380Ssam 499185380Ssam /* When we are not selecting, we are expecting an event. */ 500185380Ssam u8 event; 501187831Ssam#define ESP_EVENT_NONE 0x00 502185380Ssam#define ESP_EVENT_CMD_START 0x01 503185380Ssam#define ESP_EVENT_CMD_DONE 0x02 504185380Ssam#define ESP_EVENT_DATA_IN 0x03 505185380Ssam#define ESP_EVENT_DATA_OUT 0x04 506185380Ssam#define ESP_EVENT_DATA_DONE 0x05 507185380Ssam#define ESP_EVENT_MSGIN 0x06 508185380Ssam#define ESP_EVENT_MSGIN_MORE 0x07 509185380Ssam#define ESP_EVENT_MSGIN_DONE 0x08 510185380Ssam#define ESP_EVENT_MSGOUT 0x09 511185380Ssam#define ESP_EVENT_MSGOUT_DONE 0x0a 512185380Ssam#define ESP_EVENT_STATUS 0x0b 513185380Ssam#define ESP_EVENT_FREE_BUS 0x0c 514185380Ssam#define ESP_EVENT_CHECK_PHASE 0x0d 515185380Ssam#define ESP_EVENT_RESET 0x10 516185380Ssam 517185380Ssam /* Probed in esp_get_clock_params() */ 518185380Ssam u32 cfact; 519185380Ssam u32 cfreq; 520185380Ssam u32 ccycle; 521185380Ssam u32 ctick; 522185380Ssam u32 neg_defp; 523185380Ssam u32 sync_defp; 524185380Ssam 525185380Ssam /* Computed in esp_reset_esp() */ 526185380Ssam u32 max_period; 527219862Sadrian u32 min_period; 528185380Ssam u32 radelay; 529185380Ssam 530185380Ssam /* ESP_CMD_SELAS command state */ 531185380Ssam u8 *cmd_bytes_ptr; 532185380Ssam int cmd_bytes_left; 533185380Ssam 534185380Ssam struct completion *eh_reset; 535185380Ssam 536185380Ssam void *dma; 537185380Ssam int dmarev; 538185380Ssam 539185380Ssam /* These are used by esp_send_pio_cmd() */ 540185380Ssam u8 __iomem *fifo_reg; 541185380Ssam int send_cmd_error; 542185380Ssam u32 send_cmd_residual; 543187831Ssam}; 544185380Ssam 545185380Ssam/* A front-end driver for the ESP chip should do the following in 546185380Ssam * it's device probe routine: 547187831Ssam * 1) Allocate the host and private area using scsi_host_alloc() 548187831Ssam * with size 'sizeof(struct esp)'. The first argument to 549187831Ssam * scsi_host_alloc() should be &scsi_esp_template. 550185380Ssam * 2) Set host->max_id as appropriate. 551185380Ssam * 3) Set esp->host to the scsi_host itself, and esp->dev 552187831Ssam * to the device object pointer. 553187831Ssam * 4) Hook up esp->ops to the front-end implementation. 554187831Ssam * 5) If the ESP chip supports wide transfers, set ESP_FLAG_WIDE_CAPABLE 555187831Ssam * in esp->flags. 556187831Ssam * 6) Map the DMA and ESP chip registers. 557187831Ssam * 7) DMA map the ESP command block, store the DMA address 558187831Ssam * in esp->command_block_dma. 559187831Ssam * 8) Register the scsi_esp_intr() interrupt handler. 560187831Ssam * 9) Probe for and provide the following chip properties: 561185380Ssam * esp->scsi_id (assign to esp->host->this_id too) 562185380Ssam * esp->scsi_id_mask 563187831Ssam * If ESP bus is differential, set ESP_FLAG_DIFFERENTIAL 564187831Ssam * esp->cfreq 565187831Ssam * DMA burst bit mask in esp->bursts, if necessary 566185380Ssam * 10) Perform any actions necessary before the ESP device can 567187831Ssam * be programmed for the first time. On some configs, for 568187831Ssam * example, the DMA engine has to be reset before ESP can 569187831Ssam * be programmed. 570185380Ssam * 11) If necessary, call dev_set_drvdata() as needed. 571185380Ssam * 12) Call scsi_esp_register() with prepared 'esp' structure. 572185380Ssam * 13) Check scsi_esp_register() return value, release all resources 573185380Ssam * if an error was returned. 574185380Ssam */ 575185380Ssamextern const struct scsi_host_template scsi_esp_template; 576224514Sadrianextern int scsi_esp_register(struct esp *); 577224514Sadrian 578224514Sadrianextern void scsi_esp_unregister(struct esp *); 579185380Ssamextern irqreturn_t scsi_esp_intr(int, void *); 580224514Sadrianextern void scsi_esp_cmd(struct esp *, u8); 581224514Sadrian 582224514Sadrianextern void esp_send_pio_cmd(struct esp *esp, u32 dma_addr, u32 esp_count, 583224514Sadrian u32 dma_count, int write, u8 cmd); 584224514Sadrian 585224514Sadrian#endif /* !(_ESP_SCSI_H) */ 586224514Sadrian