Searched refs:pin (Results 276 - 300 of 826) sorted by relevance

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/linux-master/drivers/net/ethernet/broadcom/bnxt/
H A Dbnxt_ptp.c270 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage) argument
279 if (!TSIO_PIN_VALID(pin)) {
280 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n");
289 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2);
295 *(pin_state + (pin * 2)) = state;
296 *(pin_usg + (pin * 2)) = usage;
302 ptp->pps_info.pins[pin].usage = usage;
303 ptp->pps_info.pins[pin].state = state;
364 u32 pin local
766 bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin, enum ptp_pin_function func, unsigned int chan) argument
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/linux-master/drivers/pinctrl/
H A Dpinctrl-ingenic.c3311 * JZ4730 function and IRQ registers support two-bits-per-pin
3572 unsigned int pin, unsigned int reg, bool set)
3574 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3575 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3595 unsigned int pin, u8 reg, bool set)
3597 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3604 unsigned int pin)
3607 pin / PINS_PER_GPIO_CHIP);
3611 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value)
3614 * JZ4730 function and IRQ registers support two-bits-per-pin
3571 ingenic_config_pin(struct ingenic_pinctrl *jzpc, unsigned int pin, unsigned int reg, bool set) argument
3594 ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, unsigned int pin, u8 reg, bool set) argument
3603 ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, unsigned int pin) argument
3610 jz4730_config_pin_function(struct ingenic_pinctrl *jzpc, unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value) argument
3626 ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, unsigned int pin, unsigned int reg) argument
3642 unsigned int pin = gc->base + offset; local
3714 ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, int pin, int func) argument
3781 ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin, bool input) argument
3822 ingenic_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) argument
3918 ingenic_set_bias(struct ingenic_pinctrl *jzpc, unsigned int pin, unsigned int bias) argument
3966 ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc, unsigned int pin, bool enable) argument
3975 ingenic_set_output_level(struct ingenic_pinctrl *jzpc, unsigned int pin, bool high) argument
3986 ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc, unsigned int pin, unsigned int slew) argument
3995 ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) argument
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H A Dpinctrl-amd.c639 * We must read the pin register again, in case the
721 unsigned int pin,
731 pin_reg = readl(gpio_dev->base + pin*4);
761 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, argument
776 pin_reg = readl(gpio_dev->base + pin*4);
780 ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
806 writel(pin_reg, gpio_dev->base + pin*4);
850 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, argument
855 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
876 int pin local
720 amd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) argument
893 amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) argument
919 int pin = desc->pins[i].number; local
949 int pin = desc->pins[i].number; local
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H A Dpinctrl-k210.c81 * @pins: 48 32-bits IO pin registers
130 * the pin subsystem, contain no pins. The power domain groups only exist
496 u32 pin, u32 func)
503 dev_dbg(pdata->dev, "set pin %u function %s (%u) -> 0x%08x\n",
504 pin, info->name, func, val);
506 writel(val, &pdata->fpioa->pins[pin]);
510 unsigned int pin,
514 u32 val = readl(&pdata->fpioa->pins[pin]);
517 dev_dbg(pdata->dev, "set pin %u param %u, arg 0x%x\n",
518 pin, para
495 k210_pinmux_set_pin_function(struct pinctrl_dev *pctldev, u32 pin, u32 func) argument
509 k210_pinconf_set_param(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int param, unsigned int arg) argument
596 k210_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) argument
616 k210_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) argument
802 u32 pin = FIELD_GET(K210_PG_PIN, pinmux_group); local
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H A Dpinctrl-lantiq.h46 const unsigned int pin; member in struct:ltq_mfp_pin
103 int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
H A Dpinctrl-cy8c95x0.c3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
109 * On Intel Galileo Gen 1 board the IRQ pin is provided
147 * @pctldev: pin controller device
148 * @pinctrl_desc: pin controller description
318 unsigned int pin, bool input);
320 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) argument
323 return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
326 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) argument
329 return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
1008 dev_err(dev, "failed to add GPIO pin rang
1243 cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) argument
1331 cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) argument
1340 cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, unsigned int pin, bool input) argument
1366 cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin, bool input) argument
1385 cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) argument
1393 cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) argument
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/linux-master/arch/mips/pci/
H A Dpci-bcm1480.c65 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) argument
67 if (pin == 0)
70 return K_BCM1480_INT_PCI_INTA - 1 + pin;
H A Dfixup-malta.c42 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) argument
45 virq = irq_tab[slot][pin];
103 /* Mux SERIRQ to its pin */
H A Dpci-xtalk-bridge.c60 /* emulate sane interrupt pin value */
309 int pin = d->hwirq; local
316 bridge_write(data->bc, b_int_addr[pin].addr,
352 irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip,
379 int pin = irqd->hwirq; local
382 bridge_write(bc, b_int_addr[pin].addr,
385 bridge_set(bc, b_int_enable, (1 << pin));
390 * low transition of the interrupt pin.
395 bridge_set(bc, b_int_mode, (1UL << pin));
402 device &= ~(7 << (pin*
435 bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) argument
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/linux-master/arch/mips/alchemy/
H A Dboard-gpr.c241 static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) argument
243 if ((slot == 0) && (pin == 1))
245 else if ((slot == 0) && (pin == 2))
/linux-master/drivers/leds/
H A Dleds-netxbig.c70 int pin; local
72 for (pin = 0; pin < gpio_ext->num_addr; pin++)
73 gpiod_set_value(gpio_ext->addr[pin], (addr >> pin) & 1);
78 int pin; local
80 for (pin = 0; pin < gpio_ext->num_data; pin
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/linux-master/drivers/pinctrl/samsung/
H A Dpinctrl-s3c64xx.c197 * @drvdata: pin controller driver data
199 * @pins: pin offsets inside of banks of particular EINT0 interrupts
209 * @bank: pin bank related to the domain
219 * @drvdata: pin controller driver data
268 struct samsung_pin_bank *bank, int pin)
277 /* Make sure that pin is configured as interrupt */
279 shift = pin;
416 unsigned int pin; local
421 pin = svc & SVC_NUM_MASK;
426 /* Group 1 is used for two pin bank
267 s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d, struct samsung_pin_bank *bank, int pin) argument
732 unsigned int pin; local
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H A Dpinctrl-samsung.c3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
188 ret = of_property_read_u32(np, "samsung,pin-function", &val);
283 static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
288 samsung_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) argument
355 pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata, unsigned pin, void __iomem **reg, u32 *offset, struct samsung_pin_bank **bank) argument
428 samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config, bool set) argument
473 samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned num_configs) argument
488 samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) argument
872 int pin, bank, ret; local
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/linux-master/arch/arm/mach-s3c/
H A Dgpio-samsung.c619 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin) argument
621 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
624 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin) argument
626 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
797 * pinctrl-samsung driver is used, providing both GPIO and pin control
820 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) argument
822 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
830 offset = pin
871 s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull) argument
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/linux-master/sound/soc/samsung/
H A Dlowland.c24 .pin = "Headphone",
28 .pin = "Headset Mic",
32 .pin = "Line Out",
/linux-master/include/linux/ssb/
H A Dssb_driver_pci.h15 #define SSB_PCICORE_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
17 #define SSB_PCICORE_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
98 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
125 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) argument
/linux-master/arch/alpha/kernel/
H A Dsys_dp264.c376 dp264_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) argument
398 monet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) argument
430 int slot, pin = *pinp; local
447 pin = pci_swizzle_interrupt_pin(dev, pin);
455 *pinp = pin;
460 webbrick_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) argument
482 clipper_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) argument
/linux-master/arch/arm/kernel/
H A Dbios32.c346 * Swizzle the device pin each time we cross a bridge. If a platform does
352 * root bus and the interrupt pin on that device which should correspond
355 * Platforms may override this, in which case the slot and pin returned
360 static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin) argument
363 int slot, oldpin = *pin;
366 slot = sys->swizzle(dev, pin);
368 slot = pci_common_swizzle(dev, pin);
371 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
372 pci_name(dev), oldpin, *pin, slo
380 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) argument
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/linux-master/sound/soc/
H A Dsoc-component.c158 const char *pin)
162 return snd_soc_dapm_enable_pin(dapm, pin);
167 const char *pin)
171 return snd_soc_dapm_enable_pin_unlocked(dapm, pin);
176 const char *pin)
180 return snd_soc_dapm_disable_pin(dapm, pin);
185 const char *pin)
189 return snd_soc_dapm_disable_pin_unlocked(dapm, pin);
194 const char *pin)
198 return snd_soc_dapm_nc_pin(dapm, pin);
157 snd_soc_component_enable_pin(struct snd_soc_component *component, const char *pin) argument
166 snd_soc_component_enable_pin_unlocked(struct snd_soc_component *component, const char *pin) argument
175 snd_soc_component_disable_pin(struct snd_soc_component *component, const char *pin) argument
184 snd_soc_component_disable_pin_unlocked(struct snd_soc_component *component, const char *pin) argument
193 snd_soc_component_nc_pin(struct snd_soc_component *component, const char *pin) argument
202 snd_soc_component_nc_pin_unlocked(struct snd_soc_component *component, const char *pin) argument
211 snd_soc_component_get_pin_status(struct snd_soc_component *component, const char *pin) argument
220 snd_soc_component_force_enable_pin(struct snd_soc_component *component, const char *pin) argument
229 snd_soc_component_force_enable_pin_unlocked( struct snd_soc_component *component, const char *pin) argument
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/linux-master/sound/soc/intel/boards/
H A Dsof_sdw_cs42l42.c41 .pin = "Headphone",
45 .pin = "Headset Mic",
H A Dsof_sdw_rt700.c40 .pin = "Headphones",
44 .pin = "AMIC",
H A Dsof_sdw_rt5682.c40 .pin = "Headphone",
44 .pin = "Headset Mic",
/linux-master/arch/powerpc/platforms/52xx/
H A Dlite5200.c105 port_config &= ~0x00800000; /* 48Mhz internal, pin is GPIO */
124 u8 pin = 1; /* GPIO_WKUP_1 (GPIO_PSC2_4) */ local
126 mpc52xx_set_wakeup_gpio(pin, level);
/linux-master/drivers/staging/media/ipu3/
H A Dipu3-css-params.c370 unsigned int output_width, pin, s; local
422 for (pin = 0; pin < IMGU_ABI_OSYS_PINS; pin++) {
428 frame_params[pin].flip = 0;
429 frame_params[pin].mirror = 0;
430 frame_params[pin].reduce_range = 0;
431 if (reso.pin_width[pin] != 0 && reso.pin_height[pin] != 0) {
433 if (pin
855 unsigned int pin, s; local
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/linux-master/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7110.c53 * | din | dout | doen | function | pin |
97 struct seq_file *s, unsigned int pin)
104 if (pin < sfp->gc.ngpio) {
105 unsigned int offset = 4 * (pin / 4);
106 unsigned int shift = 8 * (pin % 4);
210 dev_err(dev, "error parsing pin config of group %s: %d\n",
253 void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin, argument
258 unsigned int offset = 4 * (pin / 4);
259 unsigned int shift = 8 * (pin % 4);
277 ival = (pin
96 jh7110_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) argument
351 jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp, unsigned int pin, u32 mask, u32 value) argument
375 jh7110_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) argument
518 jh7110_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) argument
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