Searched refs:barrier (Results 276 - 300 of 545) sorted by relevance
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| /linux-master/arch/parisc/include/asm/ |
| H A D | atomic.h | 11 #include <asm/barrier.h>
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| H A D | processor.h | 277 #define cpu_relax() barrier()
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| /linux-master/arch/arm/mm/ |
| H A D | cache-fa.S | 97 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
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| /linux-master/arch/arc/include/asm/ |
| H A D | io.h | 15 #include <asm/barrier.h>
214 * Relaxed API for drivers which can handle barrier ordering themselves
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| /linux-master/arch/m68k/atari/ |
| H A D | atakeyb.c | 553 barrier();
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| /linux-master/arch/mips/include/asm/ |
| H A D | bitops.h | 20 #include <asm/barrier.h>
113 * not contain a memory barrier, so if it is used for locking purposes,
206 * It also implies a memory barrier.
221 * It also implies a memory barrier.
258 * It also implies a memory barrier.
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| /linux-master/arch/parisc/kernel/ |
| H A D | smp.c | 393 barrier();
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| /linux-master/arch/powerpc/include/asm/ |
| H A D | bitops.h | 62 #include <asm/barrier.h>
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| /linux-master/arch/alpha/include/asm/ |
| H A D | bitops.h | 10 #include <asm/barrier.h>
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| /linux-master/arch/s390/include/asm/ |
| H A D | bitops.h | 40 #include <asm/barrier.h>
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| H A D | processor.h | 275 #define cpu_relax() barrier()
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| /linux-master/arch/arm64/kvm/hyp/nvhe/ |
| H A D | switch.c | 18 #include <asm/barrier.h>
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| /linux-master/arch/arm64/kvm/hyp/vhe/ |
| H A D | switch.c | 18 #include <asm/barrier.h>
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| /linux-master/arch/powerpc/kexec/ |
| H A D | core_64.c | 190 barrier();
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| /linux-master/drivers/char/hw_random/ |
| H A D | virtio-rng.c | 7 #include <asm/barrier.h>
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| /linux-master/arch/arm64/kernel/ |
| H A D | stacktrace.c | 325 barrier();
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| /linux-master/arch/arm/kernel/ |
| H A D | vdso.c | 20 #include <asm/barrier.h>
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| /linux-master/fs/xfs/ |
| H A D | xfs_linux.h | 132 * Return the address of a label. Use barrier() so that the optimizer
136 #define __this_address ({ __label__ __here; __here: barrier(); &&__here; })
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| /linux-master/drivers/hwtracing/coresight/ |
| H A D | coresight-etb10.c | 434 const u32 *barrier; local
531 barrier = coresight_barrier_pkt;
538 read_data = *barrier;
539 barrier++;
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| /linux-master/arch/riscv/include/asm/ |
| H A D | bitops.h | 15 #include <asm/barrier.h>
254 * It also implies a memory barrier.
311 * This operation is atomic and provides acquire barrier semantics.
325 * This operation is atomic and provides release barrier semantics.
339 * It does provide release barrier semantics so it can be used to unlock
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| /linux-master/drivers/scsi/ |
| H A D | vmw_pvscsi.c | 653 * barrier usage : Since the PVSCSI device is emulated, there could be cases
669 * This barrier() ensures that *e is not dereferenced while
674 barrier();
677 * This barrier() ensures that compiler doesn't reorder write
682 barrier();
767 barrier();
1108 barrier();
1110 barrier();
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| /linux-master/arch/arm/mach-omap2/ |
| H A D | sram242x.S | 138 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
167 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
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| H A D | sram243x.S | 138 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
167 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
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| /linux-master/drivers/net/ethernet/dec/tulip/ |
| H A D | media.c | 72 barrier();
131 barrier();
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| /linux-master/arch/x86/events/intel/ |
| H A D | bts.c | 214 * Since BTS is coherent, just add compiler barrier to ensure
217 barrier();
229 * - is ordered against bts::handle::event with a compiler barrier.
248 * local barrier to make sure that ds configuration made it
506 barrier();
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