1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 *  S390 version
4 *    Copyright IBM Corp. 1999
5 *    Author(s): Hartmut Penner (hp@de.ibm.com),
6 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 *  Derived from "include/asm-i386/processor.h"
9 *    Copyright (C) 1994, Linus Torvalds
10 */
11
12#ifndef __ASM_S390_PROCESSOR_H
13#define __ASM_S390_PROCESSOR_H
14
15#include <linux/bits.h>
16
17#define CIF_SIE			0	/* CPU needs SIE exit cleanup */
18#define CIF_NOHZ_DELAY		2	/* delay HZ disable for a tick */
19#define CIF_ENABLED_WAIT	5	/* in enabled wait state */
20#define CIF_MCCK_GUEST		6	/* machine check happening in guest */
21#define CIF_DEDICATED_CPU	7	/* this CPU is dedicated */
22
23#define _CIF_SIE		BIT(CIF_SIE)
24#define _CIF_NOHZ_DELAY		BIT(CIF_NOHZ_DELAY)
25#define _CIF_ENABLED_WAIT	BIT(CIF_ENABLED_WAIT)
26#define _CIF_MCCK_GUEST		BIT(CIF_MCCK_GUEST)
27#define _CIF_DEDICATED_CPU	BIT(CIF_DEDICATED_CPU)
28
29#define RESTART_FLAG_CTLREGS	_AC(1 << 0, U)
30
31#ifndef __ASSEMBLY__
32
33#include <linux/cpumask.h>
34#include <linux/linkage.h>
35#include <linux/irqflags.h>
36#include <asm/fpu-types.h>
37#include <asm/cpu.h>
38#include <asm/page.h>
39#include <asm/ptrace.h>
40#include <asm/setup.h>
41#include <asm/runtime_instr.h>
42#include <asm/irqflags.h>
43
44typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
45
46static __always_inline void set_cpu_flag(int flag)
47{
48	S390_lowcore.cpu_flags |= (1UL << flag);
49}
50
51static __always_inline void clear_cpu_flag(int flag)
52{
53	S390_lowcore.cpu_flags &= ~(1UL << flag);
54}
55
56static __always_inline bool test_cpu_flag(int flag)
57{
58	return S390_lowcore.cpu_flags & (1UL << flag);
59}
60
61static __always_inline bool test_and_set_cpu_flag(int flag)
62{
63	if (test_cpu_flag(flag))
64		return true;
65	set_cpu_flag(flag);
66	return false;
67}
68
69static __always_inline bool test_and_clear_cpu_flag(int flag)
70{
71	if (!test_cpu_flag(flag))
72		return false;
73	clear_cpu_flag(flag);
74	return true;
75}
76
77/*
78 * Test CIF flag of another CPU. The caller needs to ensure that
79 * CPU hotplug can not happen, e.g. by disabling preemption.
80 */
81static __always_inline bool test_cpu_flag_of(int flag, int cpu)
82{
83	struct lowcore *lc = lowcore_ptr[cpu];
84
85	return lc->cpu_flags & (1UL << flag);
86}
87
88#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
89
90static inline void get_cpu_id(struct cpuid *ptr)
91{
92	asm volatile("stidp %0" : "=Q" (*ptr));
93}
94
95void s390_adjust_jiffies(void);
96void s390_update_cpu_mhz(void);
97void cpu_detect_mhz_feature(void);
98
99extern const struct seq_operations cpuinfo_op;
100extern void execve_tail(void);
101unsigned long vdso_size(void);
102
103/*
104 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
105 */
106
107#define TASK_SIZE		(test_thread_flag(TIF_31BIT) ? \
108					_REGION3_SIZE : TASK_SIZE_MAX)
109#define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
110					(_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
111#define TASK_SIZE_MAX		(-PAGE_SIZE)
112
113#define VDSO_BASE		(STACK_TOP + PAGE_SIZE)
114#define VDSO_LIMIT		(test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE)
115#define STACK_TOP		(VDSO_LIMIT - vdso_size() - PAGE_SIZE)
116#define STACK_TOP_MAX		(_REGION2_SIZE - vdso_size() - PAGE_SIZE)
117
118#define HAVE_ARCH_PICK_MMAP_LAYOUT
119
120#define __stackleak_poison __stackleak_poison
121static __always_inline void __stackleak_poison(unsigned long erase_low,
122					       unsigned long erase_high,
123					       unsigned long poison)
124{
125	unsigned long tmp, count;
126
127	count = erase_high - erase_low;
128	if (!count)
129		return;
130	asm volatile(
131		"	cghi	%[count],8\n"
132		"	je	2f\n"
133		"	aghi	%[count],-(8+1)\n"
134		"	srlg	%[tmp],%[count],8\n"
135		"	ltgr	%[tmp],%[tmp]\n"
136		"	jz	1f\n"
137		"0:	stg	%[poison],0(%[addr])\n"
138		"	mvc	8(256-8,%[addr]),0(%[addr])\n"
139		"	la	%[addr],256(%[addr])\n"
140		"	brctg	%[tmp],0b\n"
141		"1:	stg	%[poison],0(%[addr])\n"
142		"	larl	%[tmp],3f\n"
143		"	ex	%[count],0(%[tmp])\n"
144		"	j	4f\n"
145		"2:	stg	%[poison],0(%[addr])\n"
146		"	j	4f\n"
147		"3:	mvc	8(1,%[addr]),0(%[addr])\n"
148		"4:\n"
149		: [addr] "+&a" (erase_low), [count] "+&d" (count), [tmp] "=&a" (tmp)
150		: [poison] "d" (poison)
151		: "memory", "cc"
152		);
153}
154
155/*
156 * Thread structure
157 */
158struct thread_struct {
159	unsigned int  acrs[NUM_ACRS];
160	unsigned long ksp;			/* kernel stack pointer */
161	unsigned long user_timer;		/* task cputime in user space */
162	unsigned long guest_timer;		/* task cputime in kvm guest */
163	unsigned long system_timer;		/* task cputime in kernel space */
164	unsigned long hardirq_timer;		/* task cputime in hardirq context */
165	unsigned long softirq_timer;		/* task cputime in softirq context */
166	const sys_call_ptr_t *sys_call_table;	/* system call table address */
167	unsigned long gmap_addr;		/* address of last gmap fault. */
168	unsigned int gmap_write_flag;		/* gmap fault write indication */
169	unsigned int gmap_int_code;		/* int code of last gmap fault */
170	unsigned int gmap_pfault;		/* signal of a pending guest pfault */
171	int ufpu_flags;				/* user fpu flags */
172	int kfpu_flags;				/* kernel fpu flags */
173
174	/* Per-thread information related to debugging */
175	struct per_regs per_user;		/* User specified PER registers */
176	struct per_event per_event;		/* Cause of the last PER trap */
177	unsigned long per_flags;		/* Flags to control debug behavior */
178	unsigned int system_call;		/* system call number in signal */
179	unsigned long last_break;		/* last breaking-event-address. */
180	/* pfault_wait is used to block the process on a pfault event */
181	unsigned long pfault_wait;
182	struct list_head list;
183	/* cpu runtime instrumentation */
184	struct runtime_instr_cb *ri_cb;
185	struct gs_cb *gs_cb;			/* Current guarded storage cb */
186	struct gs_cb *gs_bc_cb;			/* Broadcast guarded storage cb */
187	struct pgm_tdb trap_tdb;		/* Transaction abort diagnose block */
188	struct fpu ufpu;			/* User FP and VX register save area */
189	struct fpu kfpu;			/* Kernel FP and VX register save area */
190};
191
192/* Flag to disable transactions. */
193#define PER_FLAG_NO_TE			1UL
194/* Flag to enable random transaction aborts. */
195#define PER_FLAG_TE_ABORT_RAND		2UL
196/* Flag to specify random transaction abort mode:
197 * - abort each transaction at a random instruction before TEND if set.
198 * - abort random transactions at a random instruction if cleared.
199 */
200#define PER_FLAG_TE_ABORT_RAND_TEND	4UL
201
202typedef struct thread_struct thread_struct;
203
204#define ARCH_MIN_TASKALIGN	8
205
206#define INIT_THREAD {							\
207	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
208	.last_break = 1,						\
209}
210
211/*
212 * Do necessary setup to start up a new thread.
213 */
214#define start_thread(regs, new_psw, new_stackp) do {			\
215	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
216	regs->psw.addr	= new_psw;					\
217	regs->gprs[15]	= new_stackp;					\
218	execve_tail();							\
219} while (0)
220
221#define start_thread31(regs, new_psw, new_stackp) do {			\
222	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
223	regs->psw.addr	= new_psw;					\
224	regs->gprs[15]	= new_stackp;					\
225	execve_tail();							\
226} while (0)
227
228struct task_struct;
229struct mm_struct;
230struct seq_file;
231struct pt_regs;
232
233void show_registers(struct pt_regs *regs);
234void show_cacheinfo(struct seq_file *m);
235
236/* Free guarded storage control block */
237void guarded_storage_release(struct task_struct *tsk);
238void gs_load_bc_cb(struct pt_regs *regs);
239
240unsigned long __get_wchan(struct task_struct *p);
241#define task_pt_regs(tsk) ((struct pt_regs *) \
242        (task_stack_page(tsk) + THREAD_SIZE) - 1)
243#define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
244#define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])
245
246/* Has task runtime instrumentation enabled ? */
247#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
248
249/* avoid using global register due to gcc bug in versions < 8.4 */
250#define current_stack_pointer (__current_stack_pointer())
251
252static __always_inline unsigned long __current_stack_pointer(void)
253{
254	unsigned long sp;
255
256	asm volatile("lgr %0,15" : "=d" (sp));
257	return sp;
258}
259
260static __always_inline bool on_thread_stack(void)
261{
262	unsigned long ksp = S390_lowcore.kernel_stack;
263
264	return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1));
265}
266
267static __always_inline unsigned short stap(void)
268{
269	unsigned short cpu_address;
270
271	asm volatile("stap %0" : "=Q" (cpu_address));
272	return cpu_address;
273}
274
275#define cpu_relax() barrier()
276
277#define ECAG_CACHE_ATTRIBUTE	0
278#define ECAG_CPU_ATTRIBUTE	1
279
280static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
281{
282	unsigned long val;
283
284	asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
285	return val;
286}
287
288static inline void psw_set_key(unsigned int key)
289{
290	asm volatile("spka 0(%0)" : : "d" (key));
291}
292
293/*
294 * Set PSW to specified value.
295 */
296static inline void __load_psw(psw_t psw)
297{
298	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
299}
300
301/*
302 * Set PSW mask to specified value, while leaving the
303 * PSW addr pointing to the next instruction.
304 */
305static __always_inline void __load_psw_mask(unsigned long mask)
306{
307	unsigned long addr;
308	psw_t psw;
309
310	psw.mask = mask;
311
312	asm volatile(
313		"	larl	%0,1f\n"
314		"	stg	%0,%1\n"
315		"	lpswe	%2\n"
316		"1:"
317		: "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
318}
319
320/*
321 * Extract current PSW mask
322 */
323static inline unsigned long __extract_psw(void)
324{
325	unsigned int reg1, reg2;
326
327	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
328	return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
329}
330
331static inline unsigned long __local_mcck_save(void)
332{
333	unsigned long mask = __extract_psw();
334
335	__load_psw_mask(mask & ~PSW_MASK_MCHECK);
336	return mask & PSW_MASK_MCHECK;
337}
338
339#define local_mcck_save(mflags)			\
340do {						\
341	typecheck(unsigned long, mflags);	\
342	mflags = __local_mcck_save();		\
343} while (0)
344
345static inline void local_mcck_restore(unsigned long mflags)
346{
347	unsigned long mask = __extract_psw();
348
349	mask &= ~PSW_MASK_MCHECK;
350	__load_psw_mask(mask | mflags);
351}
352
353static inline void local_mcck_disable(void)
354{
355	__local_mcck_save();
356}
357
358static inline void local_mcck_enable(void)
359{
360	__load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
361}
362
363/*
364 * Rewind PSW instruction address by specified number of bytes.
365 */
366static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
367{
368	unsigned long mask;
369
370	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
371	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
372					  (1UL << 24) - 1;
373	return (psw.addr - ilc) & mask;
374}
375
376/*
377 * Function to drop a processor into disabled wait state
378 */
379static __always_inline void __noreturn disabled_wait(void)
380{
381	psw_t psw;
382
383	psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
384	psw.addr = _THIS_IP_;
385	__load_psw(psw);
386	while (1);
387}
388
389#define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL
390
391static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
392{
393	return arch_irqs_disabled_flags(regs->psw.mask);
394}
395
396#endif /* __ASSEMBLY__ */
397
398#endif /* __ASM_S390_PROCESSOR_H */
399