Searched refs:mask (Results 276 - 300 of 6712) sorted by last modified time

<<11121314151617181920>>

/linux-master/drivers/gpu/drm/xe/
H A Dxe_gt_mcr.c248 * Bank 0 is always valid _except_ when the bank mask is 010b.
276 u32 mask = REG_FIELD_GET(MEML3_EN_MASK, local
286 gt->steering[MSLICE].group_target = __ffs(mask);
294 gt->steering[LNCF].group_target = __ffs(mask) << 1;
350 u32 mask = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, local
352 u32 select = __ffs(mask);
582 * multicast bit from the mask when explicitly doing a write operation.
/linux-master/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_uncore.h88 i915_reg_t i915_reg, u32 mask,
93 return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,
98 i915_reg_t i915_reg, u32 mask,
103 return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,
109 u32 mask, u32 value, unsigned int fast_timeout_us,
114 return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,
87 intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t i915_reg, u32 mask, u32 value, unsigned int timeout) argument
97 intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t i915_reg, u32 mask, u32 value, unsigned int timeout) argument
108 __intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t i915_reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value) argument
/linux-master/drivers/gpu/drm/v3d/
H A Dv3d_drv.c265 u64 mask; local
284 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
285 ret = dma_set_mask_and_coherent(dev, mask);
/linux-master/drivers/gpu/drm/rockchip/
H A Drk3066_hdmi.c167 u32 mask, u32 disable, u32 enable)
169 if (mask)
170 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, disable);
187 if (mask)
188 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, enable);
165 rk3066_hdmi_upload_frame(struct rk3066_hdmi *hdmi, int setup_rc, union hdmi_infoframe *frame, u32 frame_index, u32 mask, u32 disable, u32 enable) argument
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon.h2531 #define WREG32_P(reg, val, mask) \
2534 tmp_ &= (mask); \
2535 tmp_ |= ((val) & ~(mask)); \
2540 #define WREG32_PLL_P(reg, val, mask) \
2543 tmp_ &= (mask); \
2544 tmp_ |= ((val) & ~(mask)); \
2547 #define WREG32_SMC_P(reg, val, mask) \
2550 tmp_ &= (mask); \
2551 tmp_ |= ((val) & ~(mask)); \
2952 u32 reg, u32 mask,
[all...]
H A Dr600.c1942 u32 data = 0, mask = 1 << (max_rb_num - 1); local
1945 /* mask out the RBs that don't exist on that asic */
1967 if (!(mask & disabled_rb_mask)) {
1978 mask >>= 1;
4397 u32 link_width_cntl, mask; local
4413 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4416 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4419 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4422 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4425 mask
[all...]
H A Dr300.c502 uint32_t link_width_cntl, mask; local
514 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
517 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
520 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
523 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
526 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
529 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
533 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
540 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
547 link_width_cntl |= mask;
[all...]
H A Dr100.c373 tmp |= voltage->gpio.mask;
375 tmp &= ~(voltage->gpio.mask);
382 tmp &= ~voltage->gpio.mask;
384 tmp |= voltage->gpio.mask;
/linux-master/drivers/gpu/drm/panthor/
H A Dpanthor_sched.c1699 u32 mask; member in struct:panthor_csg_slots_upd_ctx::__anon779
1710 u32 csg_id, u32 value, u32 mask)
1712 if (drm_WARN_ON(&ptdev->base, !mask) ||
1716 ctx->requests[csg_id].value = (ctx->requests[csg_id].value & ~mask) | (value & mask);
1717 ctx->requests[csg_id].mask |= mask;
1740 ctx->requests[csg_id].mask);
1749 u32 req_mask = ctx->requests[csg_id].mask, acked;
1708 csgs_upd_ctx_queue_reqs(struct panthor_device *ptdev, struct panthor_csg_slots_upd_ctx *ctx, u32 csg_id, u32 value, u32 mask) argument
H A Dpanthor_mmu.c1635 u32 mask = panthor_mmu_as_fault_mask(ptdev, as); local
1654 ptdev->mmu->as.faulty_mask |= mask;
1676 ptdev->mmu->irq.mask = new_int_mask;
1686 status &= ~mask;
H A Dpanthor_gpu.c230 * @mask: Sub-elements to power-off.
238 u64 mask, u32 timeout_us)
244 u32 mask32 = mask >> (i * 32);
254 blk_name, mask);
259 if (mask & GENMASK(31, 0))
260 gpu_write(ptdev, pwroff_reg, mask);
262 if (mask >> 32)
263 gpu_write(ptdev, pwroff_reg + 4, mask >> 32);
266 u32 mask32 = mask >> (i * 32);
276 blk_name, mask);
235 panthor_gpu_block_power_off(struct panthor_device *ptdev, const char *blk_name, u32 pwroff_reg, u32 pwrtrans_reg, u64 mask, u32 timeout_us) argument
296 panthor_gpu_block_power_on(struct panthor_device *ptdev, const char *blk_name, u32 pwron_reg, u32 pwrtrans_reg, u32 rdy_reg, u64 mask, u32 timeout_us) argument
[all...]
H A Dpanthor_gpu.h18 u32 rdy_reg, u64 mask, u32 timeout_us);
22 u64 mask, u32 timeout_us);
29 #define panthor_gpu_power_on(ptdev, type, mask, timeout_us) \
34 mask, timeout_us)
41 #define panthor_gpu_power_off(ptdev, type, mask, timeout_us) \
45 mask, timeout_us)
H A Dpanthor_device.h62 /** @mask: Current mask being applied to xxx_INT_MASK. */
63 u32 mask; member in struct:panthor_irq
307 u32 status = gpu_read(ptdev, __reg_prefix ## _INT_RAWSTAT) & pirq->mask; \
319 gpu_write(ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
326 pirq->mask = 0; \
332 static inline void panthor_ ## __name ## _irq_resume(struct panthor_irq *pirq, u32 mask) \
335 pirq->mask = mask; \
336 gpu_write(pirq->ptdev, __reg_prefix ## _INT_CLEAR, mask); \
[all...]
/linux-master/drivers/gpu/drm/omapdrm/
H A Domap_dmm_tiler.c180 dma_cap_mask_t mask; local
189 dma_cap_zero(mask);
190 dma_cap_set(DMA_MEMCPY, mask);
192 dmm->wa_dma_chan = dma_request_channel(mask, NULL, NULL);
868 /* set dma mask for device */
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dr535.c1261 dcbE.heads = disp->head.mask;
1355 u32 mask = 0; local
1358 mask |= NVKM_DPYID_PLUG;
1360 mask |= NVKM_DPYID_UNPLUG;
1362 if (mask)
1363 nvkm_event_ntfy(&disp->rm.event, i, mask);
1391 unsigned long mask = nvkm_rd32(device, 0x611ec0) & 0x000000ff; local
1394 for_each_set_bit(head, &mask, 8)
1482 disp->wndw.mask = ctrl->windowPresentMask;
1483 disp->wndw.nr = fls(disp->wndw.mask);
1617 unsigned long mask; local
[all...]
/linux-master/drivers/gpu/drm/nouveau/dispnv50/
H A Dcrc.c417 if (outp_atom->set.mask) {
/linux-master/drivers/gpu/drm/msm/registers/
H A Dgen_header.py118 def mask(low, high): function
168 known_mask |= mask(f.low, f.high)
172 print(" assert((%-40s & 0x%08x) == 0);" % (val, 0xffffffff ^ mask(0 , f.high - f.low)))
269 tab_to("#define %s__MASK" % name, "0x%08x" % mask(f.low, f.high))
275 print("\tassert(!(val & 0x%x));" % mask(0, f.shr - 1))
/linux-master/drivers/gpu/drm/msm/
H A Dmsm_gpu.h566 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) argument
568 msm_rmw(gpu->mmio + (reg << 2), mask, or);
H A Dmsm_drv.h489 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) argument
493 val &= ~mask;
/linux-master/drivers/gpu/drm/msm/dsi/
H A Ddsi_host.c665 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) argument
674 intr |= mask;
676 intr &= ~mask;
/linux-master/drivers/gpu/drm/msm/dp/
H A Ddp_catalog.c740 int isr, mask; local
745 mask = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK);
750 * informational bits about the HPD state status, so we only mask
754 return isr & (mask | ~DP_DP_HPD_INT_MASK);
/linux-master/drivers/gpu/drm/msm/disp/
H A Dmdp_kms.h36 uint32_t cur_irq_mask; /* current irq mask */
71 void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable);
/linux-master/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_plane.c985 u32 mask; local
990 mask = pstate->hwpipe->flush_mask;
993 mask |= pstate->r_hwpipe->flush_mask;
995 return mask;
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_sspp.c173 u32 mask, u8 en)
185 opmode |= mask;
187 opmode &= ~mask;
193 u32 mask, u8 en)
200 opmode |= mask;
202 opmode &= ~mask;
172 _sspp_setup_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) argument
192 _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) argument
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.c1484 u32 mask; local
1493 mask = BIT(0);
1496 mask |= BIT(1);
1499 mask |= BIT(3);
1502 mask |= BIT(6);
1505 mask |= BIT(8);
1507 OUT_RING(ring, mask);
1515 /* Operation mode mask */

Completed in 267 milliseconds

<<11121314151617181920>>