/linux-master/drivers/pinctrl/ |
H A D | pinctrl-aw9523.c | 775 gc->base = -1;
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/linux-master/drivers/pinctrl/mvebu/ |
H A D | pinctrl-armada-37xx.c | 99 void __iomem *base; member in struct:armada_37xx_pinctrl 533 writel(d->mask, info->base + reg); 546 val = readl(info->base + reg); 547 writel(val & ~d->mask, info->base + reg); 562 val = readl(info->base + reg); 563 writel(val | d->mask, info->base + reg); 576 val = readl(info->base + reg); 581 writel(val, info->base + reg); 596 val = readl(info->base + reg); 621 writel(val, info->base 1131 void __iomem *base; local [all...] |
/linux-master/drivers/pinctrl/freescale/ |
H A D | pinctrl-imx8ulp.c | 232 reg = readl(ipctl->base + pin_reg->mux_reg); 237 writel(reg, ipctl->base + pin_reg->mux_reg);
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/linux-master/drivers/pinctrl/bcm/ |
H A D | pinctrl-bcm2835.c | 80 void __iomem *base; member in struct:bcm2835_pinctrl 253 return readl(pc->base + reg); 259 writel(val, pc->base + reg); 398 .base = -1, 415 .base = -1, 1311 pc->base = devm_ioremap_resource(dev, &iomem); 1312 if (IS_ERR(pc->base)) 1313 return PTR_ERR(pc->base); 1354 pc->gpio_range.base = pc->gpio_chip.base; [all...] |
/linux-master/drivers/of/ |
H A D | unittest.c | 1875 devptr->chip.base = -1; /* dynamic allocation */ 1896 if (devptr->chip.base != -1) 2103 const char *base; local 2108 base = "/testcase-data/overlay-node/test-bus"; 2111 base = "/testcase-data/overlay-node/test-bus/i2c-test-bus"; 2117 snprintf(buf, sizeof(buf) - 1, "%s/test-unittest%d", base, nr); 3476 * Create base device tree for the overlay unittest. 3481 * and other early boot steps for the normal FDT so that the overlay base 3610 * finishing splicing the base overlay device tree into the live tree.
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/linux-master/drivers/net/ethernet/intel/igc/ |
H A D | igc_main.c | 654 /* Set DMA base address registers */ 3535 /* Select corresponding flex filter register and get base for host table. */ 6508 struct tc_query_caps_base *base) 6512 switch (base->type) { 6514 struct tc_taprio_caps *caps = base->caps; 6507 igc_tc_query_caps(struct igc_adapter *adapter, struct tc_query_caps_base *base) argument
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/linux-master/drivers/media/rc/ |
H A D | st_rc.c | 23 void __iomem *base; /* Register base address */ member in struct:st_rc_device 24 void __iomem *rx_base;/* RX Register base address */ 183 writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM); 276 rc_dev->base = devm_platform_ioremap_resource(pdev, 0); 277 if (IS_ERR(rc_dev->base)) { 278 ret = PTR_ERR(rc_dev->base); 283 rc_dev->rx_base = rc_dev->base + 0x40; 285 rc_dev->rx_base = rc_dev->base;
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H A D | sunxi-cir.c | 92 void __iomem *base; member in struct:sunxi_ir 109 status = readl(ir->base + SUNXI_IR_RXSTA_REG); 112 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); 122 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG); 167 ir->base + SUNXI_IR_CIR_REG); 197 writel(REG_CTL_MD, ir->base + SUNXI_IR_CTL_REG); 203 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); 206 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); 214 ir->base + SUNXI_IR_RXINT_REG); 217 tmp = readl(ir->base [all...] |
H A D | mtk-cir.c | 132 * @base: The mapped register i/o base 141 void __iomem *base; member in struct:mtk_ir 175 tmp = __raw_readl(ir->base + reg); 177 __raw_writel(tmp, ir->base + reg); 182 __raw_writel(val, ir->base + reg); 187 return __raw_readl(ir->base + reg); 325 ir->base = devm_platform_ioremap_resource(pdev, 0); 326 if (IS_ERR(ir->base)) 327 return PTR_ERR(ir->base); [all...] |
/linux-master/drivers/media/i2c/ |
H A D | max9286.c | 164 struct v4l2_async_connection base; member in struct:max9286_asd 171 return container_of(asd, struct max9286_asd, base); 1265 gpio->base = -1;
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/linux-master/drivers/iommu/ |
H A D | dma-iommu.c | 406 * @base: Start address of IOVA region for MSI mappings 411 * contiguous IOVA region, starting at @base, large enough to accommodate the 415 int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) argument 429 cookie->msi_iova = base; 689 dma_addr_t base = dma_range_map_min(map); local 690 if (base > domain->geometry.aperture_end || 696 base_pfn = max(base, domain->geometry.aperture_start) >> order;
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/linux-master/drivers/i2c/muxes/ |
H A D | i2c-mux-ltc4306.c | 159 data->gpiochip.base = -1;
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/linux-master/drivers/i2c/busses/ |
H A D | i2c-viai2c-zhaoxin.c | 58 void __iomem *base = i2c->base; local 66 msg->buf[i2c->xfered_len + i] = ioread8(base + ZXI2C_REG_HRDR); 74 tmp = ioread8(base + ZXI2C_REG_HCR); 75 iowrite8(tmp | ZXI2C_HCR_RST_FIFO, base + ZXI2C_REG_HCR); 80 iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HRLR); 82 iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HTLR); 85 iowrite8(msg->buf[i2c->xfered_len + i], base + ZXI2C_REG_HTDR); 90 tmp = ioread8(base + VIAI2C_REG_CR); 92 iowrite8(tmp, base 116 void __iomem *base = i2c->base; local [all...] |
H A D | i2c-viai2c-common.c | 10 while (!(readw(i2c->base + VIAI2C_REG_CSR) & VIAI2C_CSR_READY_MASK)) { 33 writew(0, i2c->base + VIAI2C_REG_CDR); 35 writew(pmsg->buf[0] & 0xFF, i2c->base + VIAI2C_REG_CDR); 39 val = readw(i2c->base + VIAI2C_REG_CR); 42 writew(val, i2c->base + VIAI2C_REG_CR); 49 writew(tcr_val, i2c->base + VIAI2C_REG_TCR); 52 val = readw(i2c->base + VIAI2C_REG_CR); 54 writew(val, i2c->base + VIAI2C_REG_CR); 67 val = readw(i2c->base + VIAI2C_REG_CR); 76 writew(val, i2c->base 138 void __iomem *base = i2c->base; local [all...] |
H A D | i2c-viai2c-common.h | 67 void __iomem *base; member in struct:viai2c
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H A D | i2c-viai2c-wmt.c | 59 writew(0, i2c->base + VIAI2C_REG_CR); 60 writew(MCR_APB_166M, i2c->base + VIAI2C_REG_MCR); 61 writew(VIAI2C_ISR_MASK_ALL, i2c->base + VIAI2C_REG_ISR); 62 writew(VIAI2C_IMR_ENABLE_ALL, i2c->base + VIAI2C_REG_IMR); 63 writew(VIAI2C_CR_ENABLE, i2c->base + VIAI2C_REG_CR); 64 readw(i2c->base + VIAI2C_REG_CSR); /* read clear */ 65 writew(VIAI2C_ISR_MASK_ALL, i2c->base + VIAI2C_REG_ISR); 68 writew(SCL_TIMEOUT(128) | TR_HS, i2c->base + VIAI2C_REG_TR); 70 writew(SCL_TIMEOUT(128) | TR_STD, i2c->base + VIAI2C_REG_TR); 124 writew(0, i2c->base [all...] |
H A D | i2c-tegra.c | 238 * @base: ioremapped registers cookie 239 * @base_phys: physical base address of the I2C controller 270 void __iomem *base; member in struct:tegra_i2c_dev 305 writel_relaxed(val, i2c_dev->base + reg); 310 return readl_relaxed(i2c_dev->base + reg); 329 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 333 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 335 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); 340 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 346 writesl(i2c_dev->base [all...] |
H A D | i2c-synquacer.c | 140 void __iomem *base; member in struct:synquacer_i2c 184 writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR); 204 writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR); 208 i2c->base + SYNQUACER_I2C_REG_FSR); 223 i2c->base + SYNQUACER_I2C_REG_CCR); 224 writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR); 237 i2c->base + SYNQUACER_I2C_REG_CCR); 238 writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR); 245 writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR); 246 writeb(0, i2c->base [all...] |
H A D | i2c-stm32f7.c | 304 * @base: virtual memory area 338 void __iomem *base; member in struct:stm32f7_i2c_dev 445 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 734 void __iomem *base = i2c_dev->base; local 737 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 762 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 766 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 769 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 773 stm32f7_i2c_clr_bits(i2c_dev->base 785 void __iomem *base = i2c_dev->base; local 796 void __iomem *base = i2c_dev->base; local 882 void __iomem *base = i2c_dev->base; local 976 void __iomem *base = i2c_dev->base; local 1142 void __iomem *base = i2c_dev->base; local 1287 void __iomem *base = i2c_dev->base; local 1334 void __iomem *base = i2c_dev->base; local 1436 void __iomem *base = i2c_dev->base; local 1511 void __iomem *base = i2c_dev->base; local 1604 void __iomem *base = i2c_dev->base; local 1876 void __iomem *base = i2c_dev->base; local 1894 void __iomem *base = i2c_dev->base; local 1984 void __iomem *base = i2c_dev->base; local 2073 void __iomem *base = i2c_dev->base; local 2090 void __iomem *base = i2c_dev->base; local 2105 void __iomem *base = i2c_dev->base; local 2126 void __iomem *base = i2c_dev->base; local [all...] |
H A D | i2c-stm32f4.c | 116 * @base: virtual memory area 126 void __iomem *base; member in struct:stm32f4_i2c_dev 146 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; 186 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); 222 i2c_dev->base + STM32F4_I2C_TRISE); 273 writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR); 293 writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1); 303 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2, 322 writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR); 344 rbuf = readl_relaxed(i2c_dev->base [all...] |
H A D | i2c-st.c | 173 * @base: virtual memory area 186 void __iomem *base; member in struct:st_i2c_dev 244 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) 247 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & 251 readl_relaxed(i2c_dev->base + SSC_RBUF); 262 st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); 263 st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); 280 writel_relaxed(val, i2c_dev->base + SSC_CLR); 284 writel_relaxed(val, i2c_dev->base + SSC_CTL); 291 writel_relaxed(val, i2c_dev->base [all...] |
H A D | i2c-riic.c | 98 void __iomem *base; member in struct:riic_dev 118 writeb(val, riic->base + riic->info->regs[offset]); 123 return readb(riic->base + riic->info->regs[offset]); 428 riic->base = devm_platform_ioremap_resource(pdev, 0); 429 if (IS_ERR(riic->base)) 430 return PTR_ERR(riic->base);
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H A D | i2c-qup.c | 226 void __iomem *base; member in struct:qup_i2c_dev 288 bus_err = readl(qup->base + QUP_I2C_STATUS); 289 qup_err = readl(qup->base + QUP_ERROR_FLAGS); 290 opflags = readl(qup->base + QUP_OPERATIONAL); 294 writel(QUP_RESET_STATE, qup->base + QUP_STATE); 303 writel(qup_err, qup->base + QUP_ERROR_FLAGS); 307 writel(bus_err, qup->base + QUP_I2C_STATUS); 326 writel(QUP_RESET_STATE, qup->base + QUP_STATE); 331 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); 343 writel(QUP_IN_SVC_FLAG, qup->base [all...] |
H A D | i2c-qcom-geni.c | 174 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); 177 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); 182 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); 187 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); 188 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 189 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); 190 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); 191 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); 195 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 196 tx_st = readl_relaxed(gi2c->se.base 233 void __iomem *base = gi2c->se.base; local [all...] |
H A D | i2c-omap.c | 180 void __iomem *base; /* virtual */ member in struct:omap_i2c_dev 268 writew_relaxed(val, omap->base + 274 return readw_relaxed(omap->base + 1373 omap->base = devm_platform_ioremap_resource(pdev, 0); 1374 if (IS_ERR(omap->base)) 1375 return PTR_ERR(omap->base); 1414 rev = readw_relaxed(omap->base + 0x04);
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