1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2012 FUJITSU SEMICONDUCTOR LIMITED 4 */ 5 6#include <linux/acpi.h> 7#include <linux/clk.h> 8#include <linux/delay.h> 9#include <linux/device.h> 10#include <linux/err.h> 11#include <linux/errno.h> 12#include <linux/i2c.h> 13#include <linux/interrupt.h> 14#include <linux/io.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/platform_device.h> 18#include <linux/sched.h> 19#include <linux/slab.h> 20#include <linux/spinlock.h> 21 22#define WAIT_PCLK(n, rate) \ 23 ndelay(DIV_ROUND_UP(DIV_ROUND_UP(1000000000, rate), n) + 10) 24 25/* I2C register address definitions */ 26#define SYNQUACER_I2C_REG_BSR (0x00 << 2) // Bus Status 27#define SYNQUACER_I2C_REG_BCR (0x01 << 2) // Bus Control 28#define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control 29#define SYNQUACER_I2C_REG_ADR (0x03 << 2) // Address 30#define SYNQUACER_I2C_REG_DAR (0x04 << 2) // Data 31#define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS 32#define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq 33#define SYNQUACER_I2C_REG_BC2R (0x07 << 2) // Bus Control 2 34 35/* I2C register bit definitions */ 36#define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer 37#define SYNQUACER_I2C_BSR_GCA BIT(1) // General Call Address 38#define SYNQUACER_I2C_BSR_AAS BIT(2) // Address as Slave 39#define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive 40#define SYNQUACER_I2C_BSR_LRB BIT(4) // Last Received Bit 41#define SYNQUACER_I2C_BSR_AL BIT(5) // Arbitration Lost 42#define SYNQUACER_I2C_BSR_RSC BIT(6) // Repeated Start Cond. 43#define SYNQUACER_I2C_BSR_BB BIT(7) // Bus Busy 44 45#define SYNQUACER_I2C_BCR_INT BIT(0) // Interrupt 46#define SYNQUACER_I2C_BCR_INTE BIT(1) // Interrupt Enable 47#define SYNQUACER_I2C_BCR_GCAA BIT(2) // Gen. Call Access Ack. 48#define SYNQUACER_I2C_BCR_ACK BIT(3) // Acknowledge 49#define SYNQUACER_I2C_BCR_MSS BIT(4) // Master Slave Select 50#define SYNQUACER_I2C_BCR_SCC BIT(5) // Start Condition Cont. 51#define SYNQUACER_I2C_BCR_BEIE BIT(6) // Bus Error Int Enable 52#define SYNQUACER_I2C_BCR_BER BIT(7) // Bus Error 53 54#define SYNQUACER_I2C_CCR_CS_MASK (0x1f) // CCR Clock Period Sel. 55#define SYNQUACER_I2C_CCR_EN BIT(5) // Enable 56#define SYNQUACER_I2C_CCR_FM BIT(6) // Speed Mode Select 57 58#define SYNQUACER_I2C_CSR_CS_MASK (0x3f) // CSR Clock Period Sel. 59 60#define SYNQUACER_I2C_BC2R_SCLL BIT(0) // SCL Low Drive 61#define SYNQUACER_I2C_BC2R_SDAL BIT(1) // SDA Low Drive 62#define SYNQUACER_I2C_BC2R_SCLS BIT(4) // SCL Status 63#define SYNQUACER_I2C_BC2R_SDAS BIT(5) // SDA Status 64 65/* PCLK frequency */ 66#define SYNQUACER_I2C_BUS_CLK_FR(rate) (((rate) / 20000000) + 1) 67 68/* STANDARD MODE frequency */ 69#define SYNQUACER_I2C_CLK_MASTER_STD(rate) \ 70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2) 71/* FAST MODE frequency */ 72#define SYNQUACER_I2C_CLK_MASTER_FAST(rate) \ 73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3) 74 75/* (clkrate <= 18000000) */ 76/* calculate the value of CS bits in CCR register on standard mode */ 77#define SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rate) \ 78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \ 79 & SYNQUACER_I2C_CCR_CS_MASK) 80 81/* calculate the value of CS bits in CSR register on standard mode */ 82#define SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rate) 0x00 83 84/* calculate the value of CS bits in CCR register on fast mode */ 85#define SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rate) \ 86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \ 87 & SYNQUACER_I2C_CCR_CS_MASK) 88 89/* calculate the value of CS bits in CSR register on fast mode */ 90#define SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rate) 0x00 91 92/* (clkrate > 18000000) */ 93/* calculate the value of CS bits in CCR register on standard mode */ 94#define SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rate) \ 95 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \ 96 & SYNQUACER_I2C_CCR_CS_MASK) 97 98/* calculate the value of CS bits in CSR register on standard mode */ 99#define SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rate) \ 100 (((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) >> 5) \ 101 & SYNQUACER_I2C_CSR_CS_MASK) 102 103/* calculate the value of CS bits in CCR register on fast mode */ 104#define SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rate) \ 105 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \ 106 & SYNQUACER_I2C_CCR_CS_MASK) 107 108/* calculate the value of CS bits in CSR register on fast mode */ 109#define SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rate) \ 110 (((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) >> 5) \ 111 & SYNQUACER_I2C_CSR_CS_MASK) 112 113/* min I2C clock frequency 14M */ 114#define SYNQUACER_I2C_MIN_CLK_RATE (14 * 1000000) 115/* max I2C clock frequency 200M */ 116#define SYNQUACER_I2C_MAX_CLK_RATE (200 * 1000000) 117/* I2C clock frequency 18M */ 118#define SYNQUACER_I2C_CLK_RATE_18M (18 * 1000000) 119 120#define SYNQUACER_I2C_SPEED_FM 400 // Fast Mode 121#define SYNQUACER_I2C_SPEED_SM 100 // Standard Mode 122 123enum i2c_state { 124 STATE_IDLE, 125 STATE_START, 126 STATE_READ, 127 STATE_WRITE 128}; 129 130struct synquacer_i2c { 131 struct completion completion; 132 133 struct i2c_msg *msg; 134 u32 msg_num; 135 u32 msg_idx; 136 u32 msg_ptr; 137 138 int irq; 139 struct device *dev; 140 void __iomem *base; 141 struct clk *pclk; 142 u32 pclkrate; 143 u32 speed_khz; 144 u32 timeout_ms; 145 enum i2c_state state; 146 struct i2c_adapter adapter; 147}; 148 149static inline int is_lastmsg(struct synquacer_i2c *i2c) 150{ 151 return i2c->msg_idx >= (i2c->msg_num - 1); 152} 153 154static inline int is_msglast(struct synquacer_i2c *i2c) 155{ 156 return i2c->msg_ptr == (i2c->msg->len - 1); 157} 158 159static inline int is_msgend(struct synquacer_i2c *i2c) 160{ 161 return i2c->msg_ptr >= i2c->msg->len; 162} 163 164static inline unsigned long calc_timeout_ms(struct synquacer_i2c *i2c, 165 struct i2c_msg *msgs, 166 int num) 167{ 168 unsigned long bit_count = 0; 169 int i; 170 171 for (i = 0; i < num; i++, msgs++) 172 bit_count += msgs->len; 173 174 return DIV_ROUND_UP((bit_count * 9 + num * 10) * 3, 200) + 10; 175} 176 177static void synquacer_i2c_stop(struct synquacer_i2c *i2c, int ret) 178{ 179 /* 180 * clear IRQ (INT=0, BER=0) 181 * set Stop Condition (MSS=0) 182 * Interrupt Disable 183 */ 184 writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR); 185 186 i2c->state = STATE_IDLE; 187 188 i2c->msg_ptr = 0; 189 i2c->msg = NULL; 190 i2c->msg_idx++; 191 i2c->msg_num = 0; 192 if (ret) 193 i2c->msg_idx = ret; 194 195 complete(&i2c->completion); 196} 197 198static void synquacer_i2c_hw_init(struct synquacer_i2c *i2c) 199{ 200 unsigned char ccr_cs, csr_cs; 201 u32 rt = i2c->pclkrate; 202 203 /* Set own Address */ 204 writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR); 205 206 /* Set PCLK frequency */ 207 writeb(SYNQUACER_I2C_BUS_CLK_FR(i2c->pclkrate), 208 i2c->base + SYNQUACER_I2C_REG_FSR); 209 210 switch (i2c->speed_khz) { 211 case SYNQUACER_I2C_SPEED_FM: 212 if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) { 213 ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rt); 214 csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rt); 215 } else { 216 ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rt); 217 csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rt); 218 } 219 220 /* Set Clock and enable, Set fast mode */ 221 writeb(ccr_cs | SYNQUACER_I2C_CCR_FM | 222 SYNQUACER_I2C_CCR_EN, 223 i2c->base + SYNQUACER_I2C_REG_CCR); 224 writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR); 225 break; 226 case SYNQUACER_I2C_SPEED_SM: 227 if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) { 228 ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rt); 229 csr_cs = SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rt); 230 } else { 231 ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rt); 232 csr_cs = SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rt); 233 } 234 235 /* Set Clock and enable, Set standard mode */ 236 writeb(ccr_cs | SYNQUACER_I2C_CCR_EN, 237 i2c->base + SYNQUACER_I2C_REG_CCR); 238 writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR); 239 break; 240 default: 241 WARN_ON(1); 242 } 243 244 /* clear IRQ (INT=0, BER=0), Interrupt Disable */ 245 writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR); 246 writeb(0, i2c->base + SYNQUACER_I2C_REG_BC2R); 247} 248 249static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c) 250{ 251 /* Disable clock */ 252 writeb(0, i2c->base + SYNQUACER_I2C_REG_CCR); 253 writeb(0, i2c->base + SYNQUACER_I2C_REG_CSR); 254 255 WAIT_PCLK(100, i2c->pclkrate); 256} 257 258static int synquacer_i2c_master_start(struct synquacer_i2c *i2c, 259 struct i2c_msg *pmsg) 260{ 261 unsigned char bsr, bcr; 262 263 writeb(i2c_8bit_addr_from_msg(pmsg), i2c->base + SYNQUACER_I2C_REG_DAR); 264 265 dev_dbg(i2c->dev, "slave:0x%02x\n", pmsg->addr); 266 267 /* Generate Start Condition */ 268 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); 269 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); 270 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); 271 272 if ((bsr & SYNQUACER_I2C_BSR_BB) && 273 !(bcr & SYNQUACER_I2C_BCR_MSS)) { 274 dev_dbg(i2c->dev, "bus is busy"); 275 return -EBUSY; 276 } 277 278 if (bsr & SYNQUACER_I2C_BSR_BB) { /* Bus is busy */ 279 dev_dbg(i2c->dev, "Continuous Start"); 280 writeb(bcr | SYNQUACER_I2C_BCR_SCC, 281 i2c->base + SYNQUACER_I2C_REG_BCR); 282 } else { 283 if (bcr & SYNQUACER_I2C_BCR_MSS) { 284 dev_dbg(i2c->dev, "not in master mode"); 285 return -EAGAIN; 286 } 287 dev_dbg(i2c->dev, "Start Condition"); 288 /* Start Condition + Enable Interrupts */ 289 writeb(bcr | SYNQUACER_I2C_BCR_MSS | 290 SYNQUACER_I2C_BCR_INTE | SYNQUACER_I2C_BCR_BEIE, 291 i2c->base + SYNQUACER_I2C_REG_BCR); 292 } 293 294 WAIT_PCLK(10, i2c->pclkrate); 295 296 /* get BSR & BCR registers */ 297 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); 298 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); 299 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); 300 301 if ((bsr & SYNQUACER_I2C_BSR_AL) || 302 !(bcr & SYNQUACER_I2C_BCR_MSS)) { 303 dev_dbg(i2c->dev, "arbitration lost\n"); 304 return -EAGAIN; 305 } 306 307 return 0; 308} 309 310static int synquacer_i2c_doxfer(struct synquacer_i2c *i2c, 311 struct i2c_msg *msgs, int num) 312{ 313 unsigned char bsr; 314 unsigned long timeout; 315 int ret; 316 317 synquacer_i2c_hw_init(i2c); 318 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); 319 if (bsr & SYNQUACER_I2C_BSR_BB) { 320 dev_err(i2c->dev, "cannot get bus (bus busy)\n"); 321 return -EBUSY; 322 } 323 324 reinit_completion(&i2c->completion); 325 326 i2c->msg = msgs; 327 i2c->msg_num = num; 328 i2c->msg_ptr = 0; 329 i2c->msg_idx = 0; 330 i2c->state = STATE_START; 331 332 ret = synquacer_i2c_master_start(i2c, i2c->msg); 333 if (ret < 0) { 334 dev_dbg(i2c->dev, "Address failed: (%d)\n", ret); 335 return ret; 336 } 337 338 timeout = wait_for_completion_timeout(&i2c->completion, 339 msecs_to_jiffies(i2c->timeout_ms)); 340 if (timeout == 0) { 341 dev_dbg(i2c->dev, "timeout\n"); 342 return -EAGAIN; 343 } 344 345 ret = i2c->msg_idx; 346 if (ret != num) { 347 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 348 return -EAGAIN; 349 } 350 351 /* wait 2 clock periods to ensure the stop has been through the bus */ 352 udelay(DIV_ROUND_UP(2 * 1000, i2c->speed_khz)); 353 354 return ret; 355} 356 357static irqreturn_t synquacer_i2c_isr(int irq, void *dev_id) 358{ 359 struct synquacer_i2c *i2c = dev_id; 360 361 unsigned char byte; 362 unsigned char bsr, bcr; 363 int ret; 364 365 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); 366 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); 367 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); 368 369 if (bcr & SYNQUACER_I2C_BCR_BER) { 370 dev_err(i2c->dev, "bus error\n"); 371 synquacer_i2c_stop(i2c, -EAGAIN); 372 goto out; 373 } 374 if ((bsr & SYNQUACER_I2C_BSR_AL) || 375 !(bcr & SYNQUACER_I2C_BCR_MSS)) { 376 dev_dbg(i2c->dev, "arbitration lost\n"); 377 synquacer_i2c_stop(i2c, -EAGAIN); 378 goto out; 379 } 380 381 switch (i2c->state) { 382 case STATE_START: 383 if (bsr & SYNQUACER_I2C_BSR_LRB) { 384 dev_dbg(i2c->dev, "ack was not received\n"); 385 synquacer_i2c_stop(i2c, -EAGAIN); 386 goto out; 387 } 388 389 if (i2c->msg->flags & I2C_M_RD) 390 i2c->state = STATE_READ; 391 else 392 i2c->state = STATE_WRITE; 393 394 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 395 synquacer_i2c_stop(i2c, 0); 396 goto out; 397 } 398 399 if (i2c->state == STATE_READ) 400 goto prepare_read; 401 fallthrough; 402 403 case STATE_WRITE: 404 if (bsr & SYNQUACER_I2C_BSR_LRB) { 405 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 406 synquacer_i2c_stop(i2c, -EAGAIN); 407 goto out; 408 } 409 410 if (!is_msgend(i2c)) { 411 writeb(i2c->msg->buf[i2c->msg_ptr++], 412 i2c->base + SYNQUACER_I2C_REG_DAR); 413 414 /* clear IRQ, and continue */ 415 writeb(SYNQUACER_I2C_BCR_BEIE | 416 SYNQUACER_I2C_BCR_MSS | 417 SYNQUACER_I2C_BCR_INTE, 418 i2c->base + SYNQUACER_I2C_REG_BCR); 419 break; 420 } 421 if (is_lastmsg(i2c)) { 422 synquacer_i2c_stop(i2c, 0); 423 break; 424 } 425 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 426 427 i2c->msg_ptr = 0; 428 i2c->msg_idx++; 429 i2c->msg++; 430 431 /* send the new start */ 432 ret = synquacer_i2c_master_start(i2c, i2c->msg); 433 if (ret < 0) { 434 dev_dbg(i2c->dev, "restart error (%d)\n", ret); 435 synquacer_i2c_stop(i2c, -EAGAIN); 436 break; 437 } 438 i2c->state = STATE_START; 439 break; 440 441 case STATE_READ: 442 byte = readb(i2c->base + SYNQUACER_I2C_REG_DAR); 443 if (!(bsr & SYNQUACER_I2C_BSR_FBT)) /* data */ 444 i2c->msg->buf[i2c->msg_ptr++] = byte; 445 else /* address */ 446 dev_dbg(i2c->dev, "address:0x%02x. ignore it.\n", byte); 447 448prepare_read: 449 if (is_msglast(i2c)) { 450 writeb(SYNQUACER_I2C_BCR_MSS | 451 SYNQUACER_I2C_BCR_BEIE | 452 SYNQUACER_I2C_BCR_INTE, 453 i2c->base + SYNQUACER_I2C_REG_BCR); 454 break; 455 } 456 if (!is_msgend(i2c)) { 457 writeb(SYNQUACER_I2C_BCR_MSS | 458 SYNQUACER_I2C_BCR_BEIE | 459 SYNQUACER_I2C_BCR_INTE | 460 SYNQUACER_I2C_BCR_ACK, 461 i2c->base + SYNQUACER_I2C_REG_BCR); 462 break; 463 } 464 if (is_lastmsg(i2c)) { 465 /* last message, send stop and complete */ 466 dev_dbg(i2c->dev, "READ: Send Stop\n"); 467 synquacer_i2c_stop(i2c, 0); 468 break; 469 } 470 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 471 472 i2c->msg_ptr = 0; 473 i2c->msg_idx++; 474 i2c->msg++; 475 476 ret = synquacer_i2c_master_start(i2c, i2c->msg); 477 if (ret < 0) { 478 dev_dbg(i2c->dev, "restart error (%d)\n", ret); 479 synquacer_i2c_stop(i2c, -EAGAIN); 480 } else { 481 i2c->state = STATE_START; 482 } 483 break; 484 default: 485 dev_err(i2c->dev, "called in err STATE (%d)\n", i2c->state); 486 break; 487 } 488 489out: 490 WAIT_PCLK(10, i2c->pclkrate); 491 return IRQ_HANDLED; 492} 493 494static int synquacer_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 495 int num) 496{ 497 struct synquacer_i2c *i2c; 498 int retry; 499 int ret; 500 501 i2c = i2c_get_adapdata(adap); 502 i2c->timeout_ms = calc_timeout_ms(i2c, msgs, num); 503 504 dev_dbg(i2c->dev, "calculated timeout %d ms\n", i2c->timeout_ms); 505 506 for (retry = 0; retry <= adap->retries; retry++) { 507 ret = synquacer_i2c_doxfer(i2c, msgs, num); 508 if (ret != -EAGAIN) 509 return ret; 510 511 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 512 513 synquacer_i2c_hw_reset(i2c); 514 } 515 return -EIO; 516} 517 518static u32 synquacer_i2c_functionality(struct i2c_adapter *adap) 519{ 520 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 521} 522 523static const struct i2c_algorithm synquacer_i2c_algo = { 524 .master_xfer = synquacer_i2c_xfer, 525 .functionality = synquacer_i2c_functionality, 526}; 527 528static const struct i2c_adapter synquacer_i2c_ops = { 529 .owner = THIS_MODULE, 530 .name = "synquacer_i2c-adapter", 531 .algo = &synquacer_i2c_algo, 532 .retries = 5, 533}; 534 535static int synquacer_i2c_probe(struct platform_device *pdev) 536{ 537 struct synquacer_i2c *i2c; 538 u32 bus_speed; 539 int ret; 540 541 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 542 if (!i2c) 543 return -ENOMEM; 544 545 bus_speed = i2c_acpi_find_bus_speed(&pdev->dev); 546 if (!bus_speed) 547 device_property_read_u32(&pdev->dev, "clock-frequency", 548 &bus_speed); 549 550 device_property_read_u32(&pdev->dev, "socionext,pclk-rate", 551 &i2c->pclkrate); 552 553 i2c->pclk = devm_clk_get(&pdev->dev, "pclk"); 554 if (PTR_ERR(i2c->pclk) == -EPROBE_DEFER) 555 return -EPROBE_DEFER; 556 if (!IS_ERR_OR_NULL(i2c->pclk)) { 557 dev_dbg(&pdev->dev, "clock source %p\n", i2c->pclk); 558 559 ret = clk_prepare_enable(i2c->pclk); 560 if (ret) 561 return dev_err_probe(&pdev->dev, ret, "failed to enable clock\n"); 562 i2c->pclkrate = clk_get_rate(i2c->pclk); 563 } 564 565 if (i2c->pclkrate < SYNQUACER_I2C_MIN_CLK_RATE || 566 i2c->pclkrate > SYNQUACER_I2C_MAX_CLK_RATE) 567 return dev_err_probe(&pdev->dev, -EINVAL, 568 "PCLK missing or out of range (%d)\n", 569 i2c->pclkrate); 570 571 i2c->base = devm_platform_ioremap_resource(pdev, 0); 572 if (IS_ERR(i2c->base)) 573 return PTR_ERR(i2c->base); 574 575 i2c->irq = platform_get_irq(pdev, 0); 576 if (i2c->irq < 0) 577 return i2c->irq; 578 579 ret = devm_request_irq(&pdev->dev, i2c->irq, synquacer_i2c_isr, 580 0, dev_name(&pdev->dev), i2c); 581 if (ret < 0) 582 return dev_err_probe(&pdev->dev, ret, "cannot claim IRQ %d\n", i2c->irq); 583 584 i2c->state = STATE_IDLE; 585 i2c->dev = &pdev->dev; 586 i2c->adapter = synquacer_i2c_ops; 587 i2c_set_adapdata(&i2c->adapter, i2c); 588 i2c->adapter.dev.parent = &pdev->dev; 589 i2c->adapter.dev.of_node = pdev->dev.of_node; 590 ACPI_COMPANION_SET(&i2c->adapter.dev, ACPI_COMPANION(&pdev->dev)); 591 i2c->adapter.nr = pdev->id; 592 init_completion(&i2c->completion); 593 594 if (bus_speed < I2C_MAX_FAST_MODE_FREQ) 595 i2c->speed_khz = SYNQUACER_I2C_SPEED_SM; 596 else 597 i2c->speed_khz = SYNQUACER_I2C_SPEED_FM; 598 599 synquacer_i2c_hw_init(i2c); 600 601 ret = i2c_add_numbered_adapter(&i2c->adapter); 602 if (ret) 603 return dev_err_probe(&pdev->dev, ret, "failed to add bus to i2c core\n"); 604 605 platform_set_drvdata(pdev, i2c); 606 607 dev_info(&pdev->dev, "%s: synquacer_i2c adapter\n", 608 dev_name(&i2c->adapter.dev)); 609 610 return 0; 611} 612 613static void synquacer_i2c_remove(struct platform_device *pdev) 614{ 615 struct synquacer_i2c *i2c = platform_get_drvdata(pdev); 616 617 i2c_del_adapter(&i2c->adapter); 618 if (!IS_ERR(i2c->pclk)) 619 clk_disable_unprepare(i2c->pclk); 620}; 621 622static const struct of_device_id synquacer_i2c_dt_ids[] __maybe_unused = { 623 { .compatible = "socionext,synquacer-i2c" }, 624 { /* sentinel */ } 625}; 626MODULE_DEVICE_TABLE(of, synquacer_i2c_dt_ids); 627 628#ifdef CONFIG_ACPI 629static const struct acpi_device_id synquacer_i2c_acpi_ids[] = { 630 { "SCX0003" }, 631 { /* sentinel */ } 632}; 633MODULE_DEVICE_TABLE(acpi, synquacer_i2c_acpi_ids); 634#endif 635 636static struct platform_driver synquacer_i2c_driver = { 637 .probe = synquacer_i2c_probe, 638 .remove_new = synquacer_i2c_remove, 639 .driver = { 640 .name = "synquacer_i2c", 641 .of_match_table = of_match_ptr(synquacer_i2c_dt_ids), 642 .acpi_match_table = ACPI_PTR(synquacer_i2c_acpi_ids), 643 }, 644}; 645module_platform_driver(synquacer_i2c_driver); 646 647MODULE_AUTHOR("Fujitsu Semiconductor Ltd"); 648MODULE_DESCRIPTION("Socionext SynQuacer I2C Driver"); 649MODULE_LICENSE("GPL v2"); 650