Searched refs:uint64_t (Results 276 - 300 of 1750) sorted by path

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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd.h41 extern uint64_t amdgpu_amdkfd_total_mem_size;
64 uint64_t va;
65 uint64_t pte_flags;
78 uint64_t va;
104 uint64_t vram_used_aligned[MAX_XCP];
166 uint32_t vmid, uint64_t gpu_addr,
234 void **mem_obj, uint64_t *gpu_addr,
247 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev);
252 uint64_t *bo_size, void *metadata_buffer,
302 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_di
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H A Damdgpu_amdkfd_aldebaran.c125 uint64_t watch_address,
H A Damdgpu_amdkfd_arcturus.c131 uint64_t data64;
132 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
H A Damdgpu_amdkfd_gc_9_4_3.c66 uint64_t data64;
67 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
331 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
336 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
463 uint64_t watch_address,
H A Damdgpu_amdkfd_gfx_v10.c66 static uint64_t get_queue_mask(struct amdgpu_device *adev,
256 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
261 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
268 lower_32_bits((uint64_t)wptr));
270 upper_32_bits((uint64_t)wptr));
380 uint64_t data64;
381 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
474 uint64_t queue_address, uint32_t pipe_id,
702 uint32_t vmid, uint64_t page_table_bas
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H A Damdgpu_amdkfd_gfx_v10.h43 uint64_t watch_address,
H A Damdgpu_amdkfd_gfx_v10_3.c66 static uint64_t get_queue_mask(struct amdgpu_device *adev,
242 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
247 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
254 lower_32_bits((uint64_t)wptr));
256 upper_32_bits((uint64_t)wptr));
366 uint64_t data64;
367 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
460 uint64_t queue_address, uint32_t pipe_id,
626 uint32_t vmid, uint64_t page_table_bas
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H A Damdgpu_amdkfd_gfx_v11.c64 static uint64_t get_queue_mask(struct amdgpu_device *adev,
227 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
232 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
239 lower_32_bits((uint64_t)wptr));
241 upper_32_bits((uint64_t)wptr));
351 uint64_t data64;
352 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
449 static bool hqd_is_occupied_v11(struct amdgpu_device *adev, uint64_t queue_address,
599 uint32_t vmid, uint64_t page_table_bas
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H A Damdgpu_amdkfd_gfx_v7.c321 uint64_t queue_address, uint32_t pipe_id,
532 uint64_t va, uint32_t vmid)
540 uint32_t vmid, uint64_t page_table_base)
H A Damdgpu_amdkfd_gfx_v8.c353 uint64_t queue_address, uint32_t pipe_id,
567 uint64_t va, uint32_t vmid)
575 uint32_t vmid, uint64_t page_table_base)
H A Damdgpu_amdkfd_gfx_v9.c72 uint64_t kgd_gfx_v9_get_queue_mask(struct amdgpu_device *adev,
270 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
275 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
391 uint64_t data64;
392 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
485 uint64_t queue_address, uint32_t pipe_id,
819 uint64_t watch_address,
914 uint32_t vmid, uint64_t page_table_base)
1124 uint32_t vmid, uint64_t tba_add
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H A Damdgpu_amdkfd_gfx_v9.h42 uint64_t queue_address, uint32_t pipe_id,
54 uint32_t vmid, uint64_t page_table_base);
58 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,
62 uint64_t kgd_gfx_v9_get_queue_mask(struct amdgpu_device *adev,
88 uint64_t watch_address,
H A Damdgpu_amdkfd_gpuvm.c58 uint64_t max_system_mem_limit;
59 uint64_t max_ttm_mem_limit;
116 uint64_t mem;
138 void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
171 uint64_t size, u32 alloc_flag, int8_t xcp_id)
173 uint64_t reserved_for_pt =
177 uint64_t vram_size = 0;
248 uint64_t size, u32 alloc_flag, int8_t xcp_id)
318 uint64_t flags = 0;
499 static uint64_t get_pte_flag
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H A Damdgpu_benchmark.c32 uint64_t saddr, uint64_t daddr, int n, s64 *time_ms)
80 uint64_t saddr, daddr;
H A Damdgpu_bo_list.c77 uint64_t total_size = 0;
H A Damdgpu_cgs.c209 uint64_t gpu_addr;
H A Damdgpu_connectors.c467 uint64_t val)
788 uint64_t value)
H A Damdgpu_cs.c181 uint64_t *chunk_array_user;
182 uint64_t *chunk_array;
188 chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t),
196 sizeof(uint64_t)*cs->in.num_chunks)) {
1030 uint64_t va_start;
1262 uint64_t seq;
1759 uint64_t addr, struct amdgpu_bo **bo,
H A Damdgpu_cs.h70 uint64_t bytes_moved_threshold;
71 uint64_t bytes_moved_vis_threshold;
72 uint64_t bytes_moved;
73 uint64_t bytes_moved_vis;
85 uint64_t addr, struct amdgpu_bo **bo,
H A Damdgpu_csa.c29 uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
31 uint64_t addr = AMDGPU_VA_RESERVED_CSA_START(adev);
67 uint64_t csa_addr, uint32_t size)
107 uint64_t csa_addr)
H A Damdgpu_csa.h31 uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev);
36 uint64_t csa_addr, uint32_t size);
39 uint64_t csa_addr);
H A Damdgpu_ctx.c749 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
754 uint64_t seq = centity->sequence;
778 uint64_t seq)
975 uint64_t ns = atomic64_read(&mgr->time_spend[hw_ip]);
H A Damdgpu_ctx.h40 uint64_t sequence;
50 uint64_t generation;
78 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
83 uint64_t seq);
H A Damdgpu_device.c163 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
462 uint64_t last;
506 uint64_t last;
1178 static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
1202 static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
1219 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
1226 static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)
1243 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
1250 static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t re
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H A Damdgpu_df.h46 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
48 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
50 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
51 int counter_idx, uint64_t *count);
52 uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);

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