1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22#include "amdgpu.h" 23#include "amdgpu_amdkfd.h" 24#include "amdgpu_amdkfd_arcturus.h" 25#include "amdgpu_amdkfd_gfx_v9.h" 26#include "amdgpu_amdkfd_aldebaran.h" 27#include "gc/gc_9_4_2_offset.h" 28#include "gc/gc_9_4_2_sh_mask.h" 29#include <uapi/linux/kfd_ioctl.h> 30 31/* 32 * Returns TRAP_EN, EXCP_EN and EXCP_REPLACE. 33 * 34 * restore_dbg_registers is ignored here but is a general interface requirement 35 * for devices that support GFXOFF and where the RLC save/restore list 36 * does not support hw registers for debugging i.e. the driver has to manually 37 * initialize the debug mode registers after it has disabled GFX off during the 38 * debug session. 39 */ 40uint32_t kgd_aldebaran_enable_debug_trap(struct amdgpu_device *adev, 41 bool restore_dbg_registers, 42 uint32_t vmid) 43{ 44 uint32_t data = 0; 45 46 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 47 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); 48 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); 49 50 return data; 51} 52 53/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */ 54static uint32_t kgd_aldebaran_disable_debug_trap(struct amdgpu_device *adev, 55 bool keep_trap_enabled, 56 uint32_t vmid) 57{ 58 uint32_t data = 0; 59 60 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, keep_trap_enabled); 61 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); 62 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); 63 64 return data; 65} 66 67static int kgd_aldebaran_validate_trap_override_request(struct amdgpu_device *adev, 68 uint32_t trap_override, 69 uint32_t *trap_mask_supported) 70{ 71 *trap_mask_supported &= KFD_DBG_TRAP_MASK_FP_INVALID | 72 KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL | 73 KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO | 74 KFD_DBG_TRAP_MASK_FP_OVERFLOW | 75 KFD_DBG_TRAP_MASK_FP_UNDERFLOW | 76 KFD_DBG_TRAP_MASK_FP_INEXACT | 77 KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO | 78 KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH | 79 KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION; 80 81 if (trap_override != KFD_DBG_TRAP_OVERRIDE_OR && 82 trap_override != KFD_DBG_TRAP_OVERRIDE_REPLACE) 83 return -EPERM; 84 85 return 0; 86} 87 88/* returns TRAP_EN, EXCP_EN and EXCP_RPLACE. */ 89static uint32_t kgd_aldebaran_set_wave_launch_trap_override(struct amdgpu_device *adev, 90 uint32_t vmid, 91 uint32_t trap_override, 92 uint32_t trap_mask_bits, 93 uint32_t trap_mask_request, 94 uint32_t *trap_mask_prev, 95 uint32_t kfd_dbg_trap_cntl_prev) 96 97{ 98 uint32_t data = 0; 99 100 *trap_mask_prev = REG_GET_FIELD(kfd_dbg_trap_cntl_prev, SPI_GDBG_PER_VMID_CNTL, EXCP_EN); 101 trap_mask_bits = (trap_mask_bits & trap_mask_request) | 102 (*trap_mask_prev & ~trap_mask_request); 103 104 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 105 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, trap_mask_bits); 106 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override); 107 108 return data; 109} 110 111uint32_t kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev, 112 uint8_t wave_launch_mode, 113 uint32_t vmid) 114{ 115 uint32_t data = 0; 116 117 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE, wave_launch_mode); 118 119 return data; 120} 121 122#define TCP_WATCH_STRIDE (regTCP_WATCH1_ADDR_H - regTCP_WATCH0_ADDR_H) 123static uint32_t kgd_gfx_aldebaran_set_address_watch( 124 struct amdgpu_device *adev, 125 uint64_t watch_address, 126 uint32_t watch_address_mask, 127 uint32_t watch_id, 128 uint32_t watch_mode, 129 uint32_t debug_vmid, 130 uint32_t inst) 131{ 132 uint32_t watch_address_high; 133 uint32_t watch_address_low; 134 uint32_t watch_address_cntl; 135 136 watch_address_cntl = 0; 137 watch_address_low = lower_32_bits(watch_address); 138 watch_address_high = upper_32_bits(watch_address) & 0xffff; 139 140 watch_address_cntl = REG_SET_FIELD(watch_address_cntl, 141 TCP_WATCH0_CNTL, 142 MODE, 143 watch_mode); 144 145 watch_address_cntl = REG_SET_FIELD(watch_address_cntl, 146 TCP_WATCH0_CNTL, 147 MASK, 148 watch_address_mask >> 6); 149 150 watch_address_cntl = REG_SET_FIELD(watch_address_cntl, 151 TCP_WATCH0_CNTL, 152 VALID, 153 1); 154 155 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) + 156 (watch_id * TCP_WATCH_STRIDE)), 157 watch_address_high); 158 159 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) + 160 (watch_id * TCP_WATCH_STRIDE)), 161 watch_address_low); 162 163 return watch_address_cntl; 164} 165 166const struct kfd2kgd_calls aldebaran_kfd2kgd = { 167 .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, 168 .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, 169 .init_interrupts = kgd_gfx_v9_init_interrupts, 170 .hqd_load = kgd_gfx_v9_hqd_load, 171 .hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load, 172 .hqd_sdma_load = kgd_arcturus_hqd_sdma_load, 173 .hqd_dump = kgd_gfx_v9_hqd_dump, 174 .hqd_sdma_dump = kgd_arcturus_hqd_sdma_dump, 175 .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, 176 .hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied, 177 .hqd_destroy = kgd_gfx_v9_hqd_destroy, 178 .hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy, 179 .wave_control_execute = kgd_gfx_v9_wave_control_execute, 180 .get_atc_vmid_pasid_mapping_info = 181 kgd_gfx_v9_get_atc_vmid_pasid_mapping_info, 182 .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base, 183 .get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy, 184 .enable_debug_trap = kgd_aldebaran_enable_debug_trap, 185 .disable_debug_trap = kgd_aldebaran_disable_debug_trap, 186 .validate_trap_override_request = kgd_aldebaran_validate_trap_override_request, 187 .set_wave_launch_trap_override = kgd_aldebaran_set_wave_launch_trap_override, 188 .set_wave_launch_mode = kgd_aldebaran_set_wave_launch_mode, 189 .set_address_watch = kgd_gfx_aldebaran_set_address_watch, 190 .clear_address_watch = kgd_gfx_v9_clear_address_watch, 191 .get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times, 192 .build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info, 193 .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, 194}; 195