/linux-master/drivers/gpu/host1x/ |
H A D | dev.h | 56 struct host1x_channel *ch, 59 struct host1x_channel *ch, 180 void host1x_ch_writel(struct host1x_channel *ch, u32 r, u32 v); 181 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r); 215 struct host1x_channel *ch) 217 return host->syncpt_op->assign_to_channel(sp, ch); 213 host1x_hw_syncpt_assign_to_channel( struct host1x *host, struct host1x_syncpt *sp, struct host1x_channel *ch) argument
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H A D | job.c | 26 struct host1x_job *host1x_job_alloc(struct host1x_channel *ch, argument 58 job->channel = ch;
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/linux-master/drivers/gpu/host1x/hw/ |
H A D | cdma_hw.c | 45 struct host1x_channel *ch = cdma_to_channel(cdma); local 55 host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, 59 host1x_ch_writel(ch, lower_32_bits(start), HOST1X_CHANNEL_DMASTART); 61 host1x_ch_writel(ch, upper_32_bits(start), HOST1X_CHANNEL_DMASTART_HI); 63 host1x_ch_writel(ch, cdma->push_buffer.pos, HOST1X_CHANNEL_DMAPUT); 65 host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMAPUT_HI); 67 host1x_ch_writel(ch, lower_32_bits(end), HOST1X_CHANNEL_DMAEND); 69 host1x_ch_writel(ch, upper_32_bits(end), HOST1X_CHANNEL_DMAEND_HI); 73 host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP | 79 host1x_ch_writel(ch, 92 struct host1x_channel *ch = cdma_to_channel(cdma); local 145 struct host1x_channel *ch = cdma_to_channel(cdma); local 156 struct host1x_channel *ch = cdma_to_channel(cdma); local 170 cdma_hw_cmdproc_stop(struct host1x *host, struct host1x_channel *ch, bool stop) argument 185 cdma_hw_teardown(struct host1x *host, struct host1x_channel *ch) argument 201 struct host1x_channel *ch = cdma_to_channel(cdma); local 229 struct host1x_channel *ch = cdma_to_channel(cdma); local 252 struct host1x_channel *ch = cdma_to_channel(cdma); local 282 struct host1x_channel *ch; local [all...] |
H A D | channel_hw.c | 191 static void host1x_enable_gather_filter(struct host1x_channel *ch) argument 194 struct host1x *host = dev_get_drvdata(ch->dev->parent); 201 host, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32)); 202 val |= BIT(ch->id % 32); 204 host, val, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32)); 206 host1x_ch_writel(ch, 289 struct host1x_channel *ch = job->channel; local 294 struct host1x *host = dev_get_drvdata(ch->dev->parent); 296 trace_host1x_channel_submit(dev_name(ch->dev), 304 err = mutex_lock_interruptible(&ch 349 host1x_channel_init(struct host1x_channel *ch, struct host1x *dev, unsigned int index) argument [all...] |
H A D | debug_hw_1x01.c | 15 struct host1x_channel *ch, 18 struct host1x_cdma *cdma = &ch->cdma; 24 dmastart = host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART); 25 dmaend = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND); 26 dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT); 27 dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET); 28 dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL); 29 cbread = host1x_sync_readl(host, HOST1X_SYNC_CBREAD(ch->id)); 30 cbstat = host1x_sync_readl(host, HOST1X_SYNC_CBSTAT(ch->id)); 32 host1x_debug_output(o, "%u-%s: ", ch 14 host1x_debug_show_channel_cdma(struct host1x *host, struct host1x_channel *ch, struct output *o) argument 71 host1x_debug_show_channel_fifo(struct host1x *host, struct host1x_channel *ch, struct output *o) argument [all...] |
H A D | debug_hw_1x06.c | 15 struct host1x_channel *ch, 18 struct host1x_cdma *cdma = &ch->cdma; 25 dmastart = host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART_HI); 28 dmastart |= host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART); 31 dmaend = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND_HI); 34 dmaend |= host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND); 36 dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT); 37 dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET); 38 dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL); 39 offset = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_OFFSE 14 host1x_debug_show_channel_cdma(struct host1x *host, struct host1x_channel *ch, struct output *o) argument 66 host1x_debug_show_channel_fifo(struct host1x *host, struct host1x_channel *ch, struct output *o) argument [all...] |
H A D | syncpt_hw.c | 95 * @ch: channel 98 * @ch, preventing other channels from incrementing the syncpoints. If @ch is 104 struct host1x_channel *ch) 110 HOST1X_SYNC_SYNCPT_CH_APP_CH(ch ? ch->id : 0xff), 103 syncpt_assign_to_channel(struct host1x_syncpt *sp, struct host1x_channel *ch) argument
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/linux-master/drivers/gpu/ipu-v3/ |
H A D | ipu-common.c | 250 #define idma_mask(ch) (1 << ((ch) & 0x1f))
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H A D | ipu-cpmem.c | 93 ipu_get_cpmem(struct ipuv3_channel *ch) argument 95 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; 97 return cpmem->base + ch->num; 100 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) argument 102 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); 126 static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs) argument 128 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); 228 void ipu_cpmem_zero(struct ipuv3_channel *ch) argument 230 struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch); 239 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, in argument 246 ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch) argument 252 ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride) argument 258 ipu_cpmem_set_high_priority(struct ipuv3_channel *ch) argument 272 ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf) argument 283 ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off) argument 292 ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride, u32 pixelformat) argument 333 ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id) argument 340 ipu_cpmem_get_burstsize(struct ipuv3_channel *ch) argument 346 ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize) argument 352 ipu_cpmem_set_block_mode(struct ipuv3_channel *ch) argument 358 ipu_cpmem_set_rotation(struct ipuv3_channel *ch, enum ipu_rotate_mode rot) argument 367 ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch, const struct ipu_rgb *rgb) argument 422 ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width) argument 455 ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format) argument 472 ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, unsigned int uv_stride, unsigned int u_offset, unsigned int v_offset) argument 622 ipu_cpmem_set_separate_alpha(struct ipuv3_channel *ch) argument 641 ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc) argument 764 ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image) argument 889 ipu_cpmem_dump(struct ipuv3_channel *ch) argument [all...] |
H A D | ipu-prv.h | 53 #define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32)) 54 #define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32)) 55 #define IPU_CHA_CUR_BUF(ch) IPU_CM_REG(0x023C + 4 * ((ch) / 32)) 61 #define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0268 + 4 * ((ch) / 32)) 62 #define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0270 + 4 * ((ch) / 3 [all...] |
/linux-master/drivers/hid/bpf/entrypoints/ |
H A D | Makefile | 78 $(BPFOBJ): $(wildcard $(LIBBPF_SRC)/*.[ch] $(LIBBPF_SRC)/Makefile) | $(LIBBPF_OUTPUT)
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/linux-master/drivers/hsi/controllers/ |
H A D | omap_ssi_port.c | 54 unsigned int ch; local 86 for (ch = 0; ch < omap_port->channels; ch++) { 87 seq_printf(m, "BUFFER_CH%d\t: 0x%08x\n", ch, 88 readl(base + SSI_SST_BUFFER_CH_REG(ch))); 113 for (ch = 0; ch < omap_port->channels; ch++) { 114 seq_printf(m, "BUFFER_CH%d\t: 0x%08x\n", ch, 958 unsigned int ch; local 1077 unsigned int ch; local [all...] |
/linux-master/drivers/hwmon/ |
H A D | ad7418.c | 66 int i, ch; local 92 for (i = 0, ch = 4; i < data->adc_max; i++, ch--) { 94 cfg | AD7418_REG_ADC_CH(ch));
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H A D | ads7828.c | 46 static inline u8 ads7828_cmd_byte(u8 cmd, int ch) argument 48 return cmd | (((ch >> 1) | (ch & 0x01) << 2) << 4);
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H A D | aspeed-g6-pwm-tach.c | 65 #define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00) 78 #define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04) 90 #define TACH_ASPEED_CTRL(ch) (((ch) * 0x10) + 0x08) 117 #define TACH_ASPEED_STS(ch) (((ch) * 0x10) + 0x0C) 405 u8 ch, index; local 409 ch [all...] |
H A D | bt1-pvt.c | 543 int ch) 547 if (ch < 0 || ch >= PVT_TEMP_CHS) 551 if (ch < 0 || ch >= PVT_VOLT_CHS) 564 u32 attr, int ch) 566 if (!pvt_hwmon_channel_is_valid(type, ch)) 584 return pvt_limit_is_visible(ch); 587 return pvt_alarm_is_visible(ch); 599 return pvt_limit_is_visible(PVT_VOLT + ch); 542 pvt_hwmon_channel_is_valid(enum hwmon_sensor_types type, int ch) argument 562 pvt_hwmon_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr, int ch) argument 711 pvt_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int ch, long *val) argument 766 pvt_hwmon_read_string(struct device *dev, enum hwmon_sensor_types type, u32 attr, int ch, const char **str) argument 795 pvt_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int ch, long val) argument [all...] |
H A D | gsc-hwmon.c | 150 const struct gsc_hwmon_channel *ch; local 157 ch = hwmon->in_ch[channel]; 160 ch = hwmon->temp_ch[channel]; 163 ch = hwmon->fan_ch[channel]; 169 sz = (ch->mode == mode_voltage_24bit) ? 3 : 2; 170 ret = regmap_bulk_read(hwmon->regmap, ch->reg, buf, sz); 178 switch (ch->mode) { 190 if (ch->vdiv[0] && ch->vdiv[1]) { 191 tmp *= (ch 235 gsc_hwmon_is_visible(const void *_data, enum hwmon_sensor_types type, u32 attr, int ch) argument 251 struct gsc_hwmon_channel *ch; local 343 const struct gsc_hwmon_channel *ch = &pdata->channels[i]; local [all...] |
H A D | max127.c | 26 #define MAX127_SET_CHANNEL(ch) (((ch) & 7) << MAX127_CTRL_SEL_SHIFT)
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H A D | max197.c | 260 int ch, ret; local 290 for (ch = 0; ch < MAX197_NUM_CH; ch++) 291 data->ctrl_bytes[ch] = (u8) ch;
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H A D | max31760.c | 24 #define STATUS_ALARM_CRIT(ch) BIT(2 + 2 * (ch)) 25 #define STATUS_ALARM_MAX(ch) BIT(3 + 2 * (ch)) 28 #define REG_TACH(ch) (0x52 + (ch) * 2) 29 #define REG_TEMP_INPUT(ch) (0x56 + (ch) * 2) 30 #define REG_TEMP_MAX(ch) (0x06 + (ch) * [all...] |
H A D | max31790.c | 19 #define MAX31790_REG_FAN_CONFIG(ch) (0x02 + (ch)) 20 #define MAX31790_REG_FAN_DYNAMICS(ch) (0x08 + (ch)) 23 #define MAX31790_REG_TACH_COUNT(ch) (0x18 + (ch) * 2) 24 #define MAX31790_REG_PWM_DUTY_CYCLE(ch) (0x30 + (ch) * 2) 25 #define MAX31790_REG_PWMOUT(ch) (0x40 + (ch) * [all...] |
H A D | max6639.c | 28 #define MAX6639_REG_TEMP(ch) (0x00 + (ch)) 32 #define MAX6639_REG_TEMP_EXT(ch) (0x05 + (ch)) 33 #define MAX6639_REG_ALERT_LIMIT(ch) (0x08 + (ch)) 34 #define MAX6639_REG_OT_LIMIT(ch) (0x0A + (ch)) 35 #define MAX6639_REG_THERM_LIMIT(ch) (0x0C + (ch)) [all...] |
H A D | mr75203.c | 77 #define VM_SDIF_DATA(vm, ch) \ 78 (VM_COM_REG_SIZE + 0x40 + 0x200 * (vm) + 0x4 * (ch))
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H A D | nct6683.c | 259 "AMD TSI Addr 9ch", 525 int ch = data->in_index[index]; local 530 reg = NCT6683_REG_MON(ch); 534 reg = NCT6683_REG_MON_LOW(ch); 538 reg = NCT6683_REG_MON_HIGH(ch); 548 int ch = data->temp_index[index]; local 556 reg = NCT6683_REG_INTEL_TEMP_MAX(ch); 559 reg = NCT6683_REG_INTEL_TEMP_CRIT(ch); 568 reg = NCT6683_REG_MON_LOW(ch); 571 reg = NCT6683_REG_TEMP_MAX(ch); 618 u8 ch = data->temp_index[i]; local [all...] |
H A D | npcm750-pwm-fan.c | 24 #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \ 25 (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch))) 26 #define NPCM7XX_PWM_REG_CMRx(base, n, ch) \ 27 (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch))) 28 #define NPCM7XX_PWM_REG_PDRx(base, n, ch) \ 29 (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch))) 693 int m, ch; local 721 for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch 733 int ch; local 887 u8 index, ch; local [all...] |