1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2014-2018 Nuvoton Technology corporation. 3 4#include <linux/clk.h> 5#include <linux/device.h> 6#include <linux/hwmon.h> 7#include <linux/hwmon-sysfs.h> 8#include <linux/interrupt.h> 9#include <linux/kernel.h> 10#include <linux/module.h> 11#include <linux/of_address.h> 12#include <linux/of_irq.h> 13#include <linux/platform_device.h> 14#include <linux/spinlock.h> 15#include <linux/sysfs.h> 16#include <linux/thermal.h> 17 18/* NPCM7XX PWM registers */ 19#define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) 20 21#define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00) 22#define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04) 23#define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08) 24#define NPCM7XX_PWM_REG_CNRx(base, n, ch) \ 25 (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch))) 26#define NPCM7XX_PWM_REG_CMRx(base, n, ch) \ 27 (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch))) 28#define NPCM7XX_PWM_REG_PDRx(base, n, ch) \ 29 (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch))) 30#define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C) 31#define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40) 32 33#define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3) 34#define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11) 35#define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15) 36#define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19) 37 38#define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2) 39#define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10) 40#define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14) 41#define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18) 42 43#define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0) 44#define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8) 45#define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12) 46#define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16) 47 48/* Define the maximum PWM channel number */ 49#define NPCM7XX_PWM_MAX_CHN_NUM 12 50#define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4 51#define NPCM7XX_PWM_MAX_MODULES 3 52 53/* Define the Counter Register, value = 100 for match 100% */ 54#define NPCM7XX_PWM_COUNTER_DEFAULT_NUM 255 55#define NPCM7XX_PWM_CMR_DEFAULT_NUM 255 56#define NPCM7XX_PWM_CMR_MAX 255 57 58/* default all PWM channels PRESCALE2 = 1 */ 59#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 0x4 60#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 0x40 61#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 0x400 62#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3 0x4000 63 64#define PWM_OUTPUT_FREQ_25KHZ 25000 65#define PWN_CNT_DEFAULT 256 66#define MIN_PRESCALE1 2 67#define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 8 68 69#define NPCM7XX_PWM_PRESCALE2_DEFAULT (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \ 70 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \ 71 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \ 72 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3) 73 74#define NPCM7XX_PWM_CTRL_MODE_DEFAULT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \ 75 NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \ 76 NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \ 77 NPCM7XX_PWM_CTRL_CH3_MODE_BIT) 78 79/* NPCM7XX FAN Tacho registers */ 80#define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) 81 82#define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00) 83#define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02) 84#define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04) 85#define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06) 86#define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08) 87#define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A) 88#define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C) 89#define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E) 90#define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10) 91#define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12) 92#define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14) 93#define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16) 94#define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18) 95#define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A) 96#define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C) 97 98#define NPCM7XX_FAN_TCKC_CLKX_NONE 0 99#define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0) 100#define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3) 101 102#define NPCM7XX_FAN_TMCTRL_TBEN BIT(6) 103#define NPCM7XX_FAN_TMCTRL_TAEN BIT(5) 104#define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4) 105#define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3) 106#define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2) 107 108#define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0) 109#define NPCM7XX_FAN_TICLR_TFCLR BIT(5) 110#define NPCM7XX_FAN_TICLR_TECLR BIT(4) 111#define NPCM7XX_FAN_TICLR_TDCLR BIT(3) 112#define NPCM7XX_FAN_TICLR_TCCLR BIT(2) 113#define NPCM7XX_FAN_TICLR_TBCLR BIT(1) 114#define NPCM7XX_FAN_TICLR_TACLR BIT(0) 115 116#define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0) 117#define NPCM7XX_FAN_TIEN_TFIEN BIT(5) 118#define NPCM7XX_FAN_TIEN_TEIEN BIT(4) 119#define NPCM7XX_FAN_TIEN_TDIEN BIT(3) 120#define NPCM7XX_FAN_TIEN_TCIEN BIT(2) 121#define NPCM7XX_FAN_TIEN_TBIEN BIT(1) 122#define NPCM7XX_FAN_TIEN_TAIEN BIT(0) 123 124#define NPCM7XX_FAN_TICTRL_TFPND BIT(5) 125#define NPCM7XX_FAN_TICTRL_TEPND BIT(4) 126#define NPCM7XX_FAN_TICTRL_TDPND BIT(3) 127#define NPCM7XX_FAN_TICTRL_TCPND BIT(2) 128#define NPCM7XX_FAN_TICTRL_TBPND BIT(1) 129#define NPCM7XX_FAN_TICTRL_TAPND BIT(0) 130 131#define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7) 132#define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6) 133#define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5) 134#define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4) 135#define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3) 136#define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2) 137#define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1) 138#define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0) 139 140/* FAN General Definition */ 141/* Define the maximum FAN channel number */ 142#define NPCM7XX_FAN_MAX_MODULE 8 143#define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2 144#define NPCM7XX_FAN_MAX_CHN_NUM 16 145 146/* 147 * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us) 148 * Timeout 94ms ~= 0x5000 149 * (The minimum FAN speed could to support ~640RPM/pulse 1, 150 * 320RPM/pulse 2, ...-- 10.6Hz) 151 */ 152#define NPCM7XX_FAN_TIMEOUT 0x5000 153#define NPCM7XX_FAN_TCNT 0xFFFF 154#define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT) 155#define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT) 156 157#define NPCM7XX_FAN_POLL_TIMER_200MS 200 158#define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION 2 159#define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT 0 160#define NPCM7XX_FAN_CLK_PRESCALE 255 161 162#define NPCM7XX_FAN_CMPA 0 163#define NPCM7XX_FAN_CMPB 1 164 165/* Obtain the fan number */ 166#define NPCM7XX_FAN_INPUT(fan, cmp) (((fan) << 1) + (cmp)) 167 168/* fan sample status */ 169#define FAN_DISABLE 0xFF 170#define FAN_INIT 0x00 171#define FAN_PREPARE_TO_GET_FIRST_CAPTURE 0x01 172#define FAN_ENOUGH_SAMPLE 0x02 173 174struct npcm_hwmon_info { 175 u32 pwm_max_channel; 176}; 177 178struct npcm7xx_fan_dev { 179 u8 fan_st_flg; 180 u8 fan_pls_per_rev; 181 u16 fan_cnt; 182 u32 fan_cnt_tmp; 183}; 184 185struct npcm7xx_cooling_device { 186 char name[THERMAL_NAME_LENGTH]; 187 struct npcm7xx_pwm_fan_data *data; 188 struct thermal_cooling_device *tcdev; 189 int pwm_port; 190 u8 *cooling_levels; 191 u8 max_state; 192 u8 cur_state; 193}; 194 195struct npcm7xx_pwm_fan_data { 196 void __iomem *pwm_base; 197 void __iomem *fan_base; 198 int pwm_modules; 199 unsigned long pwm_clk_freq; 200 unsigned long fan_clk_freq; 201 struct clk *pwm_clk; 202 struct clk *fan_clk; 203 struct mutex pwm_lock[NPCM7XX_PWM_MAX_MODULES]; 204 spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE]; 205 int fan_irq[NPCM7XX_FAN_MAX_MODULE]; 206 bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM]; 207 bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM]; 208 u32 input_clk_freq; 209 struct timer_list fan_timer; 210 struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM]; 211 struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM]; 212 const struct npcm_hwmon_info *info; 213 u8 fan_select; 214}; 215 216static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data, 217 int channel, u16 val) 218{ 219 u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 220 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 221 u32 tmp_buf, ctrl_en_bit, env_bit; 222 223 /* 224 * Config PWM Comparator register for setting duty cycle 225 */ 226 mutex_lock(&data->pwm_lock[module]); 227 228 /* write new CMR value */ 229 iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch)); 230 tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module)); 231 232 switch (pwm_ch) { 233 case 0: 234 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT; 235 env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT; 236 break; 237 case 1: 238 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT; 239 env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT; 240 break; 241 case 2: 242 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT; 243 env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT; 244 break; 245 case 3: 246 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT; 247 env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT; 248 break; 249 default: 250 mutex_unlock(&data->pwm_lock[module]); 251 return -ENODEV; 252 } 253 254 if (val == 0) { 255 /* Disable PWM */ 256 tmp_buf &= ~ctrl_en_bit; 257 tmp_buf |= env_bit; 258 } else { 259 /* Enable PWM */ 260 tmp_buf |= ctrl_en_bit; 261 tmp_buf &= ~env_bit; 262 } 263 264 iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module)); 265 mutex_unlock(&data->pwm_lock[module]); 266 267 return 0; 268} 269 270static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data, 271 u8 fan, u8 cmp) 272{ 273 u8 fan_id; 274 u8 reg_mode; 275 u8 reg_int; 276 unsigned long flags; 277 278 fan_id = NPCM7XX_FAN_INPUT(fan, cmp); 279 280 /* to check whether any fan tach is enable */ 281 if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) { 282 /* reset status */ 283 spin_lock_irqsave(&data->fan_lock[fan], flags); 284 285 data->fan_dev[fan_id].fan_st_flg = FAN_INIT; 286 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 287 288 /* 289 * the interrupt enable bits do not need to be cleared before 290 * it sets, the interrupt enable bits are cleared only on reset. 291 * the clock unit control register is behaving in the same 292 * manner that the interrupt enable register behave. 293 */ 294 if (cmp == NPCM7XX_FAN_CMPA) { 295 /* enable interrupt */ 296 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN | 297 NPCM7XX_FAN_TIEN_TEIEN), 298 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 299 300 reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB 301 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, 302 fan)); 303 304 /* start to Capture */ 305 iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base, 306 fan)); 307 } else { 308 /* enable interrupt */ 309 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN | 310 NPCM7XX_FAN_TIEN_TFIEN), 311 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 312 313 reg_mode = 314 NPCM7XX_FAN_TCKC_CLK2_APB 315 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, 316 fan)); 317 318 /* start to Capture */ 319 iowrite8(reg_mode, 320 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 321 } 322 323 spin_unlock_irqrestore(&data->fan_lock[fan], flags); 324 } 325} 326 327/* 328 * Enable a background timer to poll fan tach value, (200ms * 4) 329 * to polling all fan 330 */ 331static void npcm7xx_fan_polling(struct timer_list *t) 332{ 333 struct npcm7xx_pwm_fan_data *data; 334 int i; 335 336 data = from_timer(data, t, fan_timer); 337 338 /* 339 * Polling two module per one round, 340 * FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415 341 */ 342 for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE; 343 i = i + 4) { 344 /* clear the flag and reset the counter (TCNT) */ 345 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL, 346 NPCM7XX_FAN_REG_TICLR(data->fan_base, i)); 347 348 if (data->fan_present[i * 2]) { 349 iowrite16(NPCM7XX_FAN_TCNT, 350 NPCM7XX_FAN_REG_TCNT1(data->fan_base, i)); 351 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA); 352 } 353 if (data->fan_present[(i * 2) + 1]) { 354 iowrite16(NPCM7XX_FAN_TCNT, 355 NPCM7XX_FAN_REG_TCNT2(data->fan_base, i)); 356 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB); 357 } 358 } 359 360 data->fan_select++; 361 data->fan_select &= 0x3; 362 363 /* reset the timer interval */ 364 data->fan_timer.expires = jiffies + 365 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS); 366 add_timer(&data->fan_timer); 367} 368 369static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data, 370 u8 fan, u8 cmp, u8 fan_id, u8 flag_int, 371 u8 flag_mode, u8 flag_clear) 372{ 373 u8 reg_int; 374 u8 reg_mode; 375 u16 fan_cap; 376 377 if (cmp == NPCM7XX_FAN_CMPA) 378 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan)); 379 else 380 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan)); 381 382 /* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */ 383 iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan)); 384 385 if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) { 386 /* First capture, drop it */ 387 data->fan_dev[fan_id].fan_st_flg = 388 FAN_PREPARE_TO_GET_FIRST_CAPTURE; 389 390 /* reset counter */ 391 data->fan_dev[fan_id].fan_cnt_tmp = 0; 392 } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) { 393 /* 394 * collect the enough sample, 395 * (ex: 2 pulse fan need to get 2 sample) 396 */ 397 data->fan_dev[fan_id].fan_cnt_tmp += 398 (NPCM7XX_FAN_TCNT - fan_cap); 399 400 data->fan_dev[fan_id].fan_st_flg++; 401 } else { 402 /* get enough sample or fan disable */ 403 if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) { 404 data->fan_dev[fan_id].fan_cnt_tmp += 405 (NPCM7XX_FAN_TCNT - fan_cap); 406 407 /* compute finial average cnt per pulse */ 408 data->fan_dev[fan_id].fan_cnt = 409 data->fan_dev[fan_id].fan_cnt_tmp / 410 FAN_ENOUGH_SAMPLE; 411 412 data->fan_dev[fan_id].fan_st_flg = FAN_INIT; 413 } 414 415 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 416 417 /* disable interrupt */ 418 iowrite8((reg_int & ~flag_int), 419 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 420 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 421 422 /* stop capturing */ 423 iowrite8((reg_mode & ~flag_mode), 424 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 425 } 426} 427 428static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data, 429 u8 fan, u8 cmp, u8 flag) 430{ 431 u8 reg_int; 432 u8 reg_mode; 433 u8 flag_timeout; 434 u8 flag_cap; 435 u8 flag_clear; 436 u8 flag_int; 437 u8 flag_mode; 438 u8 fan_id; 439 440 fan_id = NPCM7XX_FAN_INPUT(fan, cmp); 441 442 if (cmp == NPCM7XX_FAN_CMPA) { 443 flag_cap = NPCM7XX_FAN_TICTRL_TAPND; 444 flag_timeout = NPCM7XX_FAN_TICTRL_TEPND; 445 flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN; 446 flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB; 447 flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR; 448 } else { 449 flag_cap = NPCM7XX_FAN_TICTRL_TBPND; 450 flag_timeout = NPCM7XX_FAN_TICTRL_TFPND; 451 flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN; 452 flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB; 453 flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR; 454 } 455 456 if (flag & flag_timeout) { 457 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 458 459 /* disable interrupt */ 460 iowrite8((reg_int & ~flag_int), 461 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 462 463 /* clear interrupt flag */ 464 iowrite8(flag_clear, 465 NPCM7XX_FAN_REG_TICLR(data->fan_base, fan)); 466 467 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 468 469 /* stop capturing */ 470 iowrite8((reg_mode & ~flag_mode), 471 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 472 473 /* 474 * If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't 475 * connect or speed is lower than 10.6Hz (320RPM/pulse2). 476 * In these situation, the RPM output should be zero. 477 */ 478 data->fan_dev[fan_id].fan_cnt = 0; 479 } else { 480 /* input capture is occurred */ 481 if (flag & flag_cap) 482 npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int, 483 flag_mode, flag_clear); 484 } 485} 486 487static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id) 488{ 489 struct npcm7xx_pwm_fan_data *data = dev_id; 490 unsigned long flags; 491 int module; 492 u8 flag; 493 494 module = irq - data->fan_irq[0]; 495 spin_lock_irqsave(&data->fan_lock[module], flags); 496 497 flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module)); 498 if (flag > 0) { 499 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag); 500 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag); 501 spin_unlock_irqrestore(&data->fan_lock[module], flags); 502 return IRQ_HANDLED; 503 } 504 505 spin_unlock_irqrestore(&data->fan_lock[module], flags); 506 507 return IRQ_NONE; 508} 509 510static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel, 511 long *val) 512{ 513 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); 514 u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 515 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 516 517 switch (attr) { 518 case hwmon_pwm_input: 519 *val = ioread32 520 (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch)); 521 return 0; 522 default: 523 return -EOPNOTSUPP; 524 } 525} 526 527static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel, 528 long val) 529{ 530 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); 531 int err; 532 533 switch (attr) { 534 case hwmon_pwm_input: 535 if (val < 0 || val > NPCM7XX_PWM_CMR_MAX) 536 return -EINVAL; 537 err = npcm7xx_pwm_config_set(data, channel, (u16)val); 538 break; 539 default: 540 err = -EOPNOTSUPP; 541 break; 542 } 543 544 return err; 545} 546 547static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel) 548{ 549 const struct npcm7xx_pwm_fan_data *data = _data; 550 551 if (!data->pwm_present[channel] || channel >= data->info->pwm_max_channel) 552 return 0; 553 554 switch (attr) { 555 case hwmon_pwm_input: 556 return 0644; 557 default: 558 return 0; 559 } 560} 561 562static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel, 563 long *val) 564{ 565 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); 566 567 switch (attr) { 568 case hwmon_fan_input: 569 *val = 0; 570 if (data->fan_dev[channel].fan_cnt <= 0) 571 return data->fan_dev[channel].fan_cnt; 572 573 /* Convert the raw reading to RPM */ 574 if (data->fan_dev[channel].fan_cnt > 0 && 575 data->fan_dev[channel].fan_pls_per_rev > 0) 576 *val = ((data->input_clk_freq * 60) / 577 (data->fan_dev[channel].fan_cnt * 578 data->fan_dev[channel].fan_pls_per_rev)); 579 return 0; 580 default: 581 return -EOPNOTSUPP; 582 } 583} 584 585static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel) 586{ 587 const struct npcm7xx_pwm_fan_data *data = _data; 588 589 if (!data->fan_present[channel]) 590 return 0; 591 592 switch (attr) { 593 case hwmon_fan_input: 594 return 0444; 595 default: 596 return 0; 597 } 598} 599 600static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type, 601 u32 attr, int channel, long *val) 602{ 603 switch (type) { 604 case hwmon_pwm: 605 return npcm7xx_read_pwm(dev, attr, channel, val); 606 case hwmon_fan: 607 return npcm7xx_read_fan(dev, attr, channel, val); 608 default: 609 return -EOPNOTSUPP; 610 } 611} 612 613static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type, 614 u32 attr, int channel, long val) 615{ 616 switch (type) { 617 case hwmon_pwm: 618 return npcm7xx_write_pwm(dev, attr, channel, val); 619 default: 620 return -EOPNOTSUPP; 621 } 622} 623 624static umode_t npcm7xx_is_visible(const void *data, 625 enum hwmon_sensor_types type, 626 u32 attr, int channel) 627{ 628 switch (type) { 629 case hwmon_pwm: 630 return npcm7xx_pwm_is_visible(data, attr, channel); 631 case hwmon_fan: 632 return npcm7xx_fan_is_visible(data, attr, channel); 633 default: 634 return 0; 635 } 636} 637 638static const struct hwmon_channel_info * const npcm7xx_info[] = { 639 HWMON_CHANNEL_INFO(pwm, 640 HWMON_PWM_INPUT, 641 HWMON_PWM_INPUT, 642 HWMON_PWM_INPUT, 643 HWMON_PWM_INPUT, 644 HWMON_PWM_INPUT, 645 HWMON_PWM_INPUT, 646 HWMON_PWM_INPUT, 647 HWMON_PWM_INPUT, 648 HWMON_PWM_INPUT, 649 HWMON_PWM_INPUT, 650 HWMON_PWM_INPUT, 651 HWMON_PWM_INPUT), 652 HWMON_CHANNEL_INFO(fan, 653 HWMON_F_INPUT, 654 HWMON_F_INPUT, 655 HWMON_F_INPUT, 656 HWMON_F_INPUT, 657 HWMON_F_INPUT, 658 HWMON_F_INPUT, 659 HWMON_F_INPUT, 660 HWMON_F_INPUT, 661 HWMON_F_INPUT, 662 HWMON_F_INPUT, 663 HWMON_F_INPUT, 664 HWMON_F_INPUT, 665 HWMON_F_INPUT, 666 HWMON_F_INPUT, 667 HWMON_F_INPUT, 668 HWMON_F_INPUT), 669 NULL 670}; 671 672static const struct hwmon_ops npcm7xx_hwmon_ops = { 673 .is_visible = npcm7xx_is_visible, 674 .read = npcm7xx_read, 675 .write = npcm7xx_write, 676}; 677 678static const struct hwmon_chip_info npcm7xx_chip_info = { 679 .ops = &npcm7xx_hwmon_ops, 680 .info = npcm7xx_info, 681}; 682 683static const struct npcm_hwmon_info npxm7xx_hwmon_info = { 684 .pwm_max_channel = 8, 685}; 686 687static const struct npcm_hwmon_info npxm8xx_hwmon_info = { 688 .pwm_max_channel = 12, 689}; 690 691static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data) 692{ 693 int m, ch; 694 u32 prescale_val, output_freq; 695 696 data->pwm_clk_freq = clk_get_rate(data->pwm_clk); 697 698 /* Adjust NPCM7xx PWMs output frequency to ~25Khz */ 699 output_freq = data->pwm_clk_freq / PWN_CNT_DEFAULT; 700 prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ); 701 702 /* If prescale_val = 0, then the prescale output clock is stopped */ 703 if (prescale_val < MIN_PRESCALE1) 704 prescale_val = MIN_PRESCALE1; 705 /* 706 * prescale_val need to decrement in one because in the PWM Prescale 707 * register the Prescale value increment by one 708 */ 709 prescale_val--; 710 711 /* Setting PWM Prescale Register value register to both modules */ 712 prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01); 713 714 for (m = 0; m < data->pwm_modules; m++) { 715 iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m)); 716 iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT, 717 NPCM7XX_PWM_REG_CSR(data->pwm_base, m)); 718 iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT, 719 NPCM7XX_PWM_REG_CR(data->pwm_base, m)); 720 721 for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) { 722 iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM, 723 NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch)); 724 } 725 } 726 727 return output_freq / ((prescale_val & 0xf) + 1); 728} 729 730static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data) 731{ 732 int md; 733 int ch; 734 int i; 735 u32 apb_clk_freq; 736 737 for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) { 738 /* stop FAN0~7 clock */ 739 iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE, 740 NPCM7XX_FAN_REG_TCKC(data->fan_base, md)); 741 742 /* disable all interrupt */ 743 iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md)); 744 745 /* clear all interrupt */ 746 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL, 747 NPCM7XX_FAN_REG_TICLR(data->fan_base, md)); 748 749 /* set FAN0~7 clock prescaler */ 750 iowrite8(NPCM7XX_FAN_CLK_PRESCALE, 751 NPCM7XX_FAN_REG_TPRSC(data->fan_base, md)); 752 753 /* set FAN0~7 mode (high-to-low transition) */ 754 iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN | 755 NPCM7XX_FAN_TMCTRL_TAEN), 756 NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md)); 757 758 /* set FAN0~7 Initial Count/Cap */ 759 iowrite16(NPCM7XX_FAN_TCNT, 760 NPCM7XX_FAN_REG_TCNT1(data->fan_base, md)); 761 iowrite16(NPCM7XX_FAN_TCNT, 762 NPCM7XX_FAN_REG_TCNT2(data->fan_base, md)); 763 764 /* set FAN0~7 compare (equal to count) */ 765 iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN), 766 NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md)); 767 768 /* set FAN0~7 compare value */ 769 iowrite16(NPCM7XX_FAN_TCPA, 770 NPCM7XX_FAN_REG_TCPA(data->fan_base, md)); 771 iowrite16(NPCM7XX_FAN_TCPB, 772 NPCM7XX_FAN_REG_TCPB(data->fan_base, md)); 773 774 /* set FAN0~7 fan input FANIN 0~15 */ 775 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT, 776 NPCM7XX_FAN_REG_TINASEL(data->fan_base, md)); 777 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT, 778 NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md)); 779 780 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) { 781 ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i; 782 data->fan_dev[ch].fan_st_flg = FAN_DISABLE; 783 data->fan_dev[ch].fan_pls_per_rev = 784 NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION; 785 data->fan_dev[ch].fan_cnt = 0; 786 } 787 } 788 789 apb_clk_freq = clk_get_rate(data->fan_clk); 790 791 /* Fan tach input clock = APB clock / prescalar, default is 255. */ 792 data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1); 793} 794 795static int 796npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev, 797 unsigned long *state) 798{ 799 struct npcm7xx_cooling_device *cdev = tcdev->devdata; 800 801 *state = cdev->max_state; 802 803 return 0; 804} 805 806static int 807npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev, 808 unsigned long *state) 809{ 810 struct npcm7xx_cooling_device *cdev = tcdev->devdata; 811 812 *state = cdev->cur_state; 813 814 return 0; 815} 816 817static int 818npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev, 819 unsigned long state) 820{ 821 struct npcm7xx_cooling_device *cdev = tcdev->devdata; 822 int ret; 823 824 if (state > cdev->max_state) 825 return -EINVAL; 826 827 cdev->cur_state = state; 828 ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port, 829 cdev->cooling_levels[cdev->cur_state]); 830 831 return ret; 832} 833 834static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = { 835 .get_max_state = npcm7xx_pwm_cz_get_max_state, 836 .get_cur_state = npcm7xx_pwm_cz_get_cur_state, 837 .set_cur_state = npcm7xx_pwm_cz_set_cur_state, 838}; 839 840static int npcm7xx_create_pwm_cooling(struct device *dev, 841 struct device_node *child, 842 struct npcm7xx_pwm_fan_data *data, 843 u32 pwm_port, u8 num_levels) 844{ 845 int ret; 846 struct npcm7xx_cooling_device *cdev; 847 848 cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); 849 if (!cdev) 850 return -ENOMEM; 851 852 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); 853 if (!cdev->cooling_levels) 854 return -ENOMEM; 855 856 cdev->max_state = num_levels - 1; 857 ret = of_property_read_u8_array(child, "cooling-levels", 858 cdev->cooling_levels, 859 num_levels); 860 if (ret) { 861 dev_err(dev, "Property 'cooling-levels' cannot be read.\n"); 862 return ret; 863 } 864 snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child, 865 pwm_port); 866 867 cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child, 868 cdev->name, cdev, &npcm7xx_pwm_cool_ops); 869 if (IS_ERR(cdev->tcdev)) 870 return PTR_ERR(cdev->tcdev); 871 872 cdev->data = data; 873 cdev->pwm_port = pwm_port; 874 875 data->cdev[pwm_port] = cdev; 876 877 return 0; 878} 879 880static int npcm7xx_en_pwm_fan(struct device *dev, 881 struct device_node *child, 882 struct npcm7xx_pwm_fan_data *data) 883{ 884 u8 *fan_ch; 885 u32 pwm_port; 886 int ret, fan_cnt; 887 u8 index, ch; 888 889 ret = of_property_read_u32(child, "reg", &pwm_port); 890 if (ret) 891 return ret; 892 893 data->pwm_present[pwm_port] = true; 894 ret = npcm7xx_pwm_config_set(data, pwm_port, 895 NPCM7XX_PWM_CMR_DEFAULT_NUM); 896 if (ret) 897 return ret; 898 899 ret = of_property_count_u8_elems(child, "cooling-levels"); 900 if (ret > 0) { 901 ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port, 902 ret); 903 if (ret) 904 return ret; 905 } 906 907 fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch"); 908 if (fan_cnt < 1) 909 return -EINVAL; 910 911 fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL); 912 if (!fan_ch) 913 return -ENOMEM; 914 915 ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt); 916 if (ret) 917 return ret; 918 919 for (ch = 0; ch < fan_cnt; ch++) { 920 index = fan_ch[ch]; 921 data->fan_present[index] = true; 922 data->fan_dev[index].fan_st_flg = FAN_INIT; 923 } 924 925 return 0; 926} 927 928static int npcm7xx_pwm_fan_probe(struct platform_device *pdev) 929{ 930 struct device *dev = &pdev->dev; 931 struct device_node *np, *child; 932 struct npcm7xx_pwm_fan_data *data; 933 struct resource *res; 934 struct device *hwmon; 935 char name[20]; 936 int ret, cnt; 937 u32 output_freq; 938 u32 i; 939 940 np = dev->of_node; 941 942 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 943 if (!data) 944 return -ENOMEM; 945 946 data->info = device_get_match_data(dev); 947 if (!data->info) 948 return -EINVAL; 949 950 data->pwm_modules = data->info->pwm_max_channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; 951 952 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); 953 if (!res) { 954 dev_err(dev, "pwm resource not found\n"); 955 return -ENODEV; 956 } 957 958 data->pwm_base = devm_ioremap_resource(dev, res); 959 dev_dbg(dev, "pwm base resource is %pR\n", res); 960 if (IS_ERR(data->pwm_base)) 961 return PTR_ERR(data->pwm_base); 962 963 data->pwm_clk = devm_clk_get(dev, "pwm"); 964 if (IS_ERR(data->pwm_clk)) { 965 dev_err(dev, "couldn't get pwm clock\n"); 966 return PTR_ERR(data->pwm_clk); 967 } 968 969 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan"); 970 if (!res) { 971 dev_err(dev, "fan resource not found\n"); 972 return -ENODEV; 973 } 974 975 data->fan_base = devm_ioremap_resource(dev, res); 976 dev_dbg(dev, "fan base resource is %pR\n", res); 977 if (IS_ERR(data->fan_base)) 978 return PTR_ERR(data->fan_base); 979 980 data->fan_clk = devm_clk_get(dev, "fan"); 981 if (IS_ERR(data->fan_clk)) { 982 dev_err(dev, "couldn't get fan clock\n"); 983 return PTR_ERR(data->fan_clk); 984 } 985 986 output_freq = npcm7xx_pwm_init(data); 987 npcm7xx_fan_init(data); 988 989 for (cnt = 0; cnt < data->pwm_modules; cnt++) 990 mutex_init(&data->pwm_lock[cnt]); 991 992 for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) { 993 spin_lock_init(&data->fan_lock[i]); 994 995 data->fan_irq[i] = platform_get_irq(pdev, i); 996 if (data->fan_irq[i] < 0) 997 return data->fan_irq[i]; 998 999 sprintf(name, "NPCM7XX-FAN-MD%d", i); 1000 ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr, 1001 0, name, (void *)data); 1002 if (ret) { 1003 dev_err(dev, "register IRQ fan%d failed\n", i); 1004 return ret; 1005 } 1006 } 1007 1008 for_each_child_of_node(np, child) { 1009 ret = npcm7xx_en_pwm_fan(dev, child, data); 1010 if (ret) { 1011 dev_err(dev, "enable pwm and fan failed\n"); 1012 of_node_put(child); 1013 return ret; 1014 } 1015 } 1016 1017 hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan", 1018 data, &npcm7xx_chip_info, 1019 NULL); 1020 if (IS_ERR(hwmon)) { 1021 dev_err(dev, "unable to register hwmon device\n"); 1022 return PTR_ERR(hwmon); 1023 } 1024 1025 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) { 1026 if (data->fan_present[i]) { 1027 /* fan timer initialization */ 1028 data->fan_timer.expires = jiffies + 1029 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS); 1030 timer_setup(&data->fan_timer, 1031 npcm7xx_fan_polling, 0); 1032 add_timer(&data->fan_timer); 1033 break; 1034 } 1035 } 1036 1037 pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n", 1038 output_freq, data->input_clk_freq); 1039 1040 return 0; 1041} 1042 1043static const struct of_device_id of_pwm_fan_match_table[] = { 1044 { .compatible = "nuvoton,npcm750-pwm-fan", .data = &npxm7xx_hwmon_info}, 1045 { .compatible = "nuvoton,npcm845-pwm-fan", .data = &npxm8xx_hwmon_info}, 1046 {}, 1047}; 1048MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table); 1049 1050static struct platform_driver npcm7xx_pwm_fan_driver = { 1051 .probe = npcm7xx_pwm_fan_probe, 1052 .driver = { 1053 .name = "npcm7xx_pwm_fan", 1054 .of_match_table = of_pwm_fan_match_table, 1055 }, 1056}; 1057 1058module_platform_driver(npcm7xx_pwm_fan_driver); 1059 1060MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver"); 1061MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); 1062MODULE_LICENSE("GPL v2"); 1063