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a94b8a77 |
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27-Jun-2022 |
Mikko Perttunen <mperttunen@nvidia.com> |
gpu: host1x: Add MLOCK release code on Tegra234 With the full-featured opcode sequence using MLOCKs, we need to also unlock those MLOCKs in the event of a timeout. However, it turns out that on Tegra186/Tegra194, by default, we don't need to do this; furthermore, on Tegra234 it is much simpler to do; so only implement this on Tegra234 for the time being. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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2aed4f5a |
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29-Mar-2021 |
Mikko Perttunen <mperttunen@nvidia.com> |
gpu: host1x: Cleanup and refcounting for syncpoints Add reference counting for allocated syncpoints to allow keeping them allocated while jobs are referencing them. Additionally, clean up various places using syncpoint IDs to use host1x_syncpt pointers instead. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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9952f691 |
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28-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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79930baf |
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07-Aug-2018 |
Dmitry Osipenko <digetx@gmail.com> |
gpu: host1x: Continue CDMA execution starting with a next job Currently gathers of a hung job are getting NOP'ed and a restarted CDMA executes the NOP'ed gathers. There shouldn't be a reason to not restart CDMA execution starting with a next job, avoiding the unnecessary churning with gathers NOP'ing. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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0e43b8da |
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01-Feb-2019 |
Thierry Reding <treding@nvidia.com> |
gpu: host1x: Use correct semantics for HOST1X_CHANNEL_DMAEND The HOST1X_CHANNEL_DMAEND is an offset relative to the value written to the HOST1X_CHANNEL_DMASTART register, but it is currently treated as an absolute address. This can cause SMMU faults if the CDMA fetches past a pushbuffer's IOMMU mapping. Properly setting the DMAEND prevents the CDMA from fetching beyond that address and avoid such issues. This is currently not observed because a whole (almost) page of essentially scratch space absorbs any excessive prefetching by CDMA. However, changing the number of slots in the push buffer can trigger these SMMU faults. Signed-off-by: Thierry Reding <treding@nvidia.com>
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67a82dbc |
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01-Feb-2019 |
Thierry Reding <treding@nvidia.com> |
gpu: host1x: Support 40-bit addressing Tegra186 and later support 40 bits of address space. Additional registers need to be programmed to store the full 40 bits of push buffer addresses. Since command stream gathers can also reside in buffers in a 40-bit address space, a new variant of the GATHER opcode is also introduced. It takes two parameters: the first parameter contains the lower 32 bits of the address and the second parameter contains bits 32 to 39. Signed-off-by: Thierry Reding <treding@nvidia.com>
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f1b53c4e |
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05-Sep-2017 |
Mikko Perttunen <mperttunen@nvidia.com> |
gpu: host1x: Add Tegra186 support Add support for the implementation of Host1x present on the Tegra186. The register space has been shuffled around a little bit, requiring addition of some chip-specific code sections. Tegra186 also adds several new features, most importantly the hypervisor, but those are not yet supported with this commit. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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404bfb78 |
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14-Dec-2016 |
Mikko Perttunen <mperttunen@nvidia.com> |
gpu: host1x: Add IOMMU support Add support for the Host1x unit to be located behind an IOMMU. This is required when gather buffers may be allocated non-contiguously in physical memory, as can be the case when TegraDRM is also using the IOMMU. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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813a9d4e |
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23-Jun-2016 |
Thierry Reding <treding@nvidia.com> |
gpu: host1x: Remove redundant parentheses There's no need to wrap the BIT() macro into an extra set of parentheses because it's already implemented to use its own set. Signed-off-by: Thierry Reding <treding@nvidia.com>
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0b8070d1 |
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23-Jun-2016 |
Thierry Reding <treding@nvidia.com> |
gpu: host1x: Whitespace cleanup for readability Insert a number of blank lines in places where they increase readability of the code. Also collapse various variable declarations to shorten some functions and finally rewrite some code for readability. Signed-off-by: Thierry Reding <treding@nvidia.com>
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5c0d8d38 |
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23-Jun-2016 |
Thierry Reding <treding@nvidia.com> |
gpu: host1x: Use unsigned int consistently for IDs IDs can never be negative so use unsigned int. In some instances an explicitly sized type (such as u32) was used for no particular reason, so turn those into unsigned int as well for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
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14c95fc8 |
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22-Jun-2016 |
Thierry Reding <treding@nvidia.com> |
gpu: host1x: Consistently use unsigned int for counts The number of channels, syncpoints, bases and mlocks can never be negative, so use unsigned int instead of int. Also make loop variables the same type for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
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ba73fbc2 |
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12-Jun-2014 |
Thierry Reding <treding@nvidia.com> |
gpu: host1x: Print address/offset pairs consistently Consistently use a format of %pad+%#x to print address/offset in debug messages. Signed-off-by: Thierry Reding <treding@nvidia.com>
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7f27d60b |
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12-Jun-2014 |
Thierry Reding <treding@nvidia.com> |
gpu: host1x: Fix typo in comment Signed-off-by: Thierry Reding <treding@nvidia.com>
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0169b93f |
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12-Jun-2014 |
Thierry Reding <treding@nvidia.com> |
gpu: host1x: Make mapped field of push buffers void * This reduces the amount of casting that needs to be done to get rid of annoying warnings on 64-bit builds. Signed-off-by: Thierry Reding <treding@nvidia.com>
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43dd5554 |
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13-Nov-2013 |
Olof Johansson <olof@lixom.net> |
gpu: host1x: Silence a few warnings with LPAE=y When building with LPAE=y (64-bit dma_addr_t), the following warnings are seen: drivers/gpu/host1x/hw/cdma_hw.c:57:3: warning: format '%x' expects argument of type 'unsigned int', but argument 5 has type 'dma_addr_t' drivers/gpu/host1x/hw/debug_hw.c:167:10: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'dma_addr_t' The agreed-to solution for this is upcast to u64 and using %llx. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
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fc3be3e8 |
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09-Oct-2013 |
Thierry Reding <treding@nvidia.com> |
gpu: host1x: Use relative include paths This is slightly safer than adding -Idrivers/gpu/host1x to cflags-y. Signed-off-by: Thierry Reding <treding@nvidia.com>
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ebae30b1 |
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29-May-2013 |
Arto Merilainen <amerilainen@nvidia.com> |
gpu: host1x: Rework CPU syncpoint increment This patch merges host1x_syncpt_cpu_incr to host1x_syncpt_incr() as they are in practise doing the same thing. host1x_syncpt_incr() is also modified to return error codes. User space interface is modified accordingly to pass return values. Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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6236451d |
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22-Mar-2013 |
Terje Bergstrom <tbergstrom@nvidia.com> |
gpu: host1x: Add debug support Add support for host1x debugging. Adds debugfs entries, and dumps channel state to UART in case of stuck job. Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Erik Faye-Lund <kusmabite@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
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6579324a |
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22-Mar-2013 |
Terje Bergstrom <tbergstrom@nvidia.com> |
gpu: host1x: Add channel support Add support for host1x client modules, and host1x channels to submit work to the clients. Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Erik Faye-Lund <kusmabite@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
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