/linux-master/arch/powerpc/perf/ |
H A D | isa207-common.c | 208 unsigned int cache; local 210 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK; 211 return cache; 403 unsigned int unit, pmc, cache, ebb; local 414 cache = (event >> EVENT_CACHE_SEL_SHIFT) & 417 cache = (event >> EVENT_CACHE_SEL_SHIFT) & 471 } else if (cache & 0x7) { 473 * L2/L3 events contain a cache selector field, which is 478 * have a cache selector of zero. The bank selector (bit 3) is 486 value |= CNST_L1_QUAL_VAL(cache); 562 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; local [all...] |
/linux-master/drivers/base/regmap/ |
H A D | regcache.c | 3 // Register cache access API 55 dev_warn(map->dev, "No cache defaults, reading back from HW\n"); 57 /* Bypass the cache access till data read from HW */ 122 "No cache used with register defaults set!\n"); 149 dev_err(map->dev, "Could not match cache type: %d\n", 160 map->cache = NULL; 179 /* Some devices such as PMICs don't have cache defaults, 181 * crafting the cache defaults by hand. 196 dev_dbg(map->dev, "Initializing %s cache\n", 224 dev_dbg(map->dev, "Destroying %s cache\ 627 u8 *cache = base; local 633 u16 *cache = base; local 639 u32 *cache = base; local 662 const u8 *cache = base; local 667 const u16 *cache = base; local 672 const u32 *cache = base; local [all...] |
/linux-master/arch/arm/mm/ |
H A D | proc-mohawk.S | 22 * area is larger than this, then we flush the whole cache. 27 * The cache line size of the L1 D cache. 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 99 * Clean and invalidate all cache entries in a particular 108 * Clean and invalidate the entire cache. 114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 123 * Clean and invalidate a range of cache entries in the 189 * Ensure no D cache aliasin [all...] |
H A D | cache-fa.S | 3 * linux/arch/arm/mm/cache-fa.S 8 * Based on cache-v4wb.S: 21 * The size of one data cache line. 26 * The total size of the data cache. 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 51 * Clean and invalidate all cache entries in a particular address 59 * Clean and invalidate the entire cache. 65 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 76 * Invalidate a range of cache entrie [all...] |
H A D | proc-xscale.S | 32 * is larger than this, then we flush the whole cache 37 * the cache line size of the I and D cache 42 * the size of the data cache 47 * Virtual address used to allocate the cache when flushed 56 * Without this the XScale core exhibits cache eviction problems and no one 91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache lin [all...] |
/linux-master/tools/lib/bpf/ |
H A D | features.c | 561 bool feat_supported(struct kern_feature_cache *cache, enum kern_feature_id feat_id) argument 566 /* assume global feature cache, unless custom one is provided */ 567 if (!cache) 568 cache = &feature_cache; 570 if (READ_ONCE(cache->res[feat_id]) == FEAT_UNKNOWN) { 571 ret = feat->probe(cache->token_fd); 573 WRITE_ONCE(cache->res[feat_id], FEAT_SUPPORTED); 575 WRITE_ONCE(cache->res[feat_id], FEAT_MISSING); 578 WRITE_ONCE(cache->res[feat_id], FEAT_MISSING); 582 return READ_ONCE(cache [all...] |
/linux-master/mm/kasan/ |
H A D | report.c | 300 " which belongs to the cache %s of size %d\n", 301 info->object, info->cache->name, info->cache->object_size); 346 kasan_print_aux_stacks(info->cache, info->object); 380 if (info->cache && info->object) { 508 info->cache = slab->slab_cache; 509 info->object = nearest_obj(info->cache, slab, addr); 512 info->alloc_size = kasan_get_alloc_size(info->object, info->cache); 515 info->alloc_size = info->cache->object_size; 517 info->cache [all...] |
/linux-master/drivers/irqchip/ |
H A D | irq-renesas-rzg2l.c | 60 * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume) 74 * @cache: Registers cache for suspend/resume 80 struct rzg2l_irqc_reg_cache cache; member in struct:rzg2l_irqc_priv 300 struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; local 303 cache->iitsr = readl_relaxed(base + IITSR); 305 cache->titsr[i] = readl_relaxed(base + TITSR(i)); 312 struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; local [all...] |
/linux-master/tools/cgroup/ |
H A D | memcg_slabinfo.py | 199 cache = slab.slab_cache 200 if not cache: 202 addr = cache.value_() 203 caches[addr] = cache 211 for i in range(oo_objects(cache)):
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/linux-master/drivers/md/bcache/ |
H A D | debug.c | 28 i = (void *) i + set_blocks(i, block_bytes(b->c->cache)) * \ 29 block_bytes(b->c->cache)) 53 bio_set_dev(bio, b->c->cache->bdev); 85 block_bytes(b->c->cache); 92 ((void *) i - (void *) ondisk) / block_bytes(b->c->cache)); 158 /* XXX: cache set refcounting */
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H A D | journal.c | 21 * them into the cache in precisely the same order as they appear in the 35 static int journal_read_bucket(struct cache *ca, struct list_head *list, 181 struct cache *ca = c->cache; 341 struct cache *ca = s->cache; 575 struct cache *ca = container_of(ja, struct cache, journal); 591 static void do_journal_discard(struct cache *ca) 633 struct cache *c [all...] |
/linux-master/scripts/ |
H A D | decode_stacktrace.sh | 72 declare -A cache 2>/dev/null 158 if [[ $aarray_support == true && "${cache[$module,$name]+isset}" == "isset" ]]; then 159 local base_addr=${cache[$module,$name]} 167 cache[$module,$name]="$base_addr" 184 if [[ $aarray_support == true && "${cache[$module,$address]+isset}" == "isset" ]]; then 185 local code=${cache[$module,$address]} 189 cache[$module,$address]=$code
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/linux-master/fs/netfs/ |
H A D | fscache_io.c | 8 #include <linux/fscache-cache.h> 17 * @cres: The cache resources for the operation being performed 20 * See if the target cache object is at the specified minimum state of 30 if (!fscache_cache_is_live(cookie->volume->cache)) { 61 return cookie->volume->cache->ops->begin_operation(cres, want_state); 67 * Begin an I/O operation on the cache, waiting till we reach the right state. 118 if (!cookie->volume->cache->ops->begin_operation(cres, want_state)) 193 * Deal with the completion of writing the data to the cache. 283 cookie->volume->cache->ops->resize_cookie(&cres, new_size);
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/linux-master/drivers/md/ |
H A D | dm-bufio.c | 368 * The buffer cache manages buffers, particularly: 377 * - Eviction or cache sizing. 448 struct dm_buffer_cache *cache; member in struct:lock_history 454 static void lh_init(struct lock_history *lh, struct dm_buffer_cache *cache, bool write) argument 456 lh->cache = cache; 458 lh->no_previous = cache->num_locks; 465 if (static_branch_unlikely(&no_sleep_enabled) && lh->cache->no_sleep) 466 write_lock_bh(&lh->cache->trees[index].u.spinlock); 468 down_write(&lh->cache 1017 struct dm_buffer_cache cache; /* must be last member */ member in struct:dm_bufio_client [all...] |
/linux-master/drivers/acpi/apei/ |
H A D | ghes.c | 774 struct ghes_estatus_cache *cache; local 780 cache = rcu_dereference(ghes_estatus_caches[i]); 781 if (cache == NULL) 783 if (len != cache->estatus_len) 785 cache_estatus = GHES_ESTATUS_FROM_CACHE(cache); 788 atomic_inc(&cache->count); 790 if (now - cache->time_in < GHES_ESTATUS_IN_CACHE_MAX_NSEC) 804 struct ghes_estatus_cache *cache; local 814 cache = (void *)gen_pool_alloc(ghes_estatus_pool, cache_len); 815 if (!cache) { 830 struct ghes_estatus_cache *cache; local 845 struct ghes_estatus_cache *cache, *new_cache; local [all...] |
/linux-master/drivers/gpu/drm/i915/ |
H A D | i915_active.c | 22 * nodes from a local slab cache to hopefully reduce the fragmentation. 141 /* Even if we have not used the cache, we may still have a barrier */ 142 if (!ref->cache) 143 ref->cache = fetch_node(ref->tree.rb_node); 146 if (ref->cache) { 148 rb_erase(&ref->cache->node, &ref->tree); 152 rb_link_node(&ref->cache->node, NULL, &ref->tree.rb_node); 153 rb_insert_color(&ref->cache->node, &ref->tree); 154 GEM_BUG_ON(ref->tree.rb_node != &ref->cache->node); 157 ref->cache [all...] |
/linux-master/kernel/bpf/ |
H A D | memalloc.c | 16 * Front-end kmalloc() with per-cpu per-bucket cache of free elements. 17 * Refill this cache asynchronously from irq_work. 27 * It's safe to allocate from cache of the current cpu with irqs disabled. 121 struct bpf_mem_cache cache[NUM_CACHES]; member in struct:bpf_mem_caches 455 * the freelist cache will be elem_size * 64 (or less) on each cpu. 481 /* When page_size == 4k, order-0 cache will have low_mark == 2 552 ma->cache = pc; 566 c = &cc->cache[i]; 615 c = &cc->cache[i]; 668 if (ma->cache) { [all...] |
/linux-master/drivers/gpu/host1x/ |
H A D | bus.c | 721 host1x_bo_cache_init(&client->cache); 809 host1x_bo_cache_destroy(&client->cache); 886 struct host1x_bo_cache *cache) 890 if (cache) { 891 mutex_lock(&cache->lock); 893 list_for_each_entry(mapping, &cache->mappings, entry) { 909 if (cache) { 911 mapping->cache = cache; 913 list_add_tail(&mapping->entry, &cache 884 host1x_bo_pin(struct device *dev, struct host1x_bo *bo, enum dma_data_direction dir, struct host1x_bo_cache *cache) argument 947 struct host1x_bo_cache *cache = mapping->cache; local [all...] |
/linux-master/arch/powerpc/boot/dts/fsl/ |
H A D | mpc8544si-post.dtsi | 167 L2: l2-cache-controller@20000 { 168 compatible = "fsl,mpc8544-l2-cache-controller"; 170 cache-line-size = <32>; // 32 bytes 171 cache-size = <0x40000>; // L2, 256K
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H A D | p1021si-post.dtsi | 136 L2: l2-cache-controller@20000 { 137 compatible = "fsl,p1021-l2-cache-controller"; 139 cache-line-size = <32>; // 32 bytes 140 cache-size = <0x40000>; // L2,256K
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/linux-master/drivers/acpi/acpica/ |
H A D | uttrack.c | 48 * PARAMETERS: cache_name - Ascii name for the cache 50 * return_cache - Where the new cache object is returned 62 struct acpi_memory_list *cache; local 64 cache = acpi_os_allocate_zeroed(sizeof(struct acpi_memory_list)); 65 if (!cache) { 69 cache->list_name = list_name; 70 cache->object_size = object_size; 72 *return_cache = cache; 580 /* Ignore allocated objects that are in a cache */ 698 ACPI_ERROR((AE_INFO, "%u (0x%X) Outstanding cache allocation [all...] |
/linux-master/arch/mips/include/asm/ |
H A D | r4kcache.h | 6 * Inline assembly cache operations. 36 * for indexed cache operations. Two issues here: 141 "1: cache %1, (%2) \n" \ 202 static inline void extra##blast_##pfx##cache##lsize(void) \ 217 static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \ 228 static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ 266 static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \ 289 static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \ 318 static inline void blast_##pfx##cache##lsize##_node(long node) \
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/linux-master/include/net/netfilter/ |
H A D | nf_conntrack_ecache.h | 3 * connection tracking event cache. 22 unsigned long cache; /* bitops want long */ member in struct:nf_conntrack_ecache 111 set_bit(event, &e->cache);
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/linux-master/arch/arm/kernel/ |
H A D | irq.c | 36 #include <asm/hardware/cache-l2x0.h> 37 #include <asm/hardware/cache-uniphier.h>
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/linux-master/arch/powerpc/lib/ |
H A D | strlen_32.S | 11 #include <asm/cache.h>
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