Searched refs:divider (Results 26 - 50 of 147) sorted by relevance

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/linux-master/drivers/i2c/busses/
H A Di2c-bcm2835.c93 u32 divider = DIV_ROUND_UP(parent_rate, rate); local
98 * if the LSB is set, increment the divider to avoid any issue.
100 if (divider & 1)
101 divider++;
102 if ((divider < BCM2835_I2C_CDIV_MIN) ||
103 (divider > BCM2835_I2C_CDIV_MAX))
106 return divider;
114 u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate); local
116 if (divider == -EINVAL)
119 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
143 u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate); local
152 u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV); local
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H A Di2c-mxs.c702 uint32_t divider; local
707 divider = DIV_ROUND_UP(clk, speed);
709 if (divider < 25) {
711 * limit the divider, so that min(low_count, high_count)
714 divider = 25;
718 clk / divider / 1000, clk / divider % 1000);
719 } else if (divider > 1897) {
721 * limit the divider, so that max(low_count, high_count)
724 divider
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/linux-master/drivers/clk/baikal-t1/
H A Dccu-div.h26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
28 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
30 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
43 * @CCU_DIV_VAR: Clocks gate with variable divider.
44 * @CCU_DIV_GATE: Clocks gate with fixed divider.
45 * @CCU_DIV_BUF: Clock gate with no divider.
46 * @CCU_DIV_FIXED: Ungateable clock with fixed divider.
63 * @type: CCU divider type (variable, fixed with and without gate).
65 * @divider: Divider fixed value.
79 unsigned int divider; member in union:ccu_div_init_data::__anon8
105 unsigned int divider; member in union:ccu_div::__anon9
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/linux-master/drivers/media/rc/
H A Dir-xmp-decoder.c75 int divider, i; local
89 * the 4th nibble should be 15 so base the divider on this
91 * the divider to compensate for fluctuations in the signal
93 divider = (n[3] - XMP_NIBBLE_PREFIX) / 15 - 2000;
94 if (divider < 50) {
95 dev_dbg(&dev->dev, "divider to small %d.\n",
96 divider);
103 n[i] = (n[i] - XMP_NIBBLE_PREFIX) / divider;
/linux-master/drivers/clk/x86/
H A Dclk-cgu.c125 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); local
128 val = lgm_get_clk_val(divider->membase, divider->reg,
129 divider->shift, divider->width);
131 return divider_recalc_rate(hw, parent_rate, val, divider->table,
132 divider->flags, divider->width);
139 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); local
141 return divider_round_rate(hw, rate, prate, divider
149 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); local
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/linux-master/drivers/media/i2c/cx25840/
H A Dcx25840-ir.c124 * Note the largest clock divider value of 0xffff corresponds to:
145 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) argument
147 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
150 static inline unsigned int clock_divider_to_freq(unsigned int divider, argument
154 (divider + 1) * rollovers);
195 static u32 clock_divider_to_resolution(u16 divider) argument
202 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
206 static u64 pulse_width_count_to_ns(u16 count, u16 divider) argument
215 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
224 static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
248 pulse_width_count_to_us(u16 count, u16 divider) argument
391 txclk_tx_s_carrier(struct i2c_client *c, unsigned int freq, u16 *divider) argument
400 rxclk_rx_s_carrier(struct i2c_client *c, unsigned int freq, u16 *divider) argument
409 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns, u16 *divider) argument
422 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns, u16 *divider) argument
633 u16 divider; local
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/linux-master/drivers/clk/davinci/
H A Dpll.c230 * @fixed: if true, the divider is a fixed value
243 struct clk_divider *divider; local
254 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
255 if (!divider) {
260 divider->reg = reg;
261 divider->shift = DIV_RATIO_SHIFT;
262 divider->width = DIV_RATIO_WIDTH;
265 divider->flags |= CLK_DIVIDER_READ_ONLY;
270 NULL, NULL, &divider
578 struct clk_divider *divider; local
682 struct clk_divider *divider; local
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/linux-master/drivers/media/pci/cx23885/
H A Dcx23888-ir.c163 * Note the largest clock divider value of 0xffff corresponds to:
184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) argument
186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
189 static inline unsigned int clock_divider_to_freq(unsigned int divider, argument
193 (divider + 1) * rollovers);
234 static u32 clock_divider_to_resolution(u16 divider) argument
241 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
245 static u64 pulse_width_count_to_ns(u16 count, u16 divider) argument
254 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
261 static unsigned int pulse_width_count_to_us(u16 count, u16 divider) argument
411 txclk_tx_s_carrier(struct cx23885_dev *dev, unsigned int freq, u16 *divider) argument
420 rxclk_rx_s_carrier(struct cx23885_dev *dev, unsigned int freq, u16 *divider) argument
429 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, u16 *divider) argument
442 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, u16 *divider) argument
634 u16 divider = (u16) atomic_read(&state->rxclk_divider); local
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/linux-master/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c118 struct clk_divider divider; member in struct:mpfs_ccc_out_hw_clock
126 .divider.shift = _shift, \
127 .divider.width = _width, \
129 .divider.flags = _flags, \
130 .divider.lock = &mpfs_ccc_lock, \
172 out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
173 out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
176 ret = devm_clk_hw_register(dev, &out_hw->divider.hw);
181 data->hw_data.hws[out_hw->id] = &out_hw->divider.hw;
/linux-master/drivers/video/fbdev/aty/
H A Dmach64_ct.c121 u32 multiplier, divider, ras_multiplier, ras_divider, tmp; local
126 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
132 divider = divider * (bpp >> 2);
144 divider = divider * pll->xres & ~7;
150 /* If we don't do this, 32 bits for multiplier & divider won't be
152 while (((multiplier | divider) & 1) == 0) {
154 divider = divider >>
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H A Dmach64_gx.c504 short divider = 0, tempA; local
521 divider = 0;
524 divider += 0x20;
542 divider &= ~0x1f;
543 divider |= tempA;
544 divider =
545 (divider & 0x00ff) +
553 program_bits = divider;
558 pll->ics2595.post_divider = divider; /* fuer nix */
743 short divider local
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/linux-master/drivers/clk/actions/
H A DMakefile7 clk-owl-y += owl-divider.o
/linux-master/drivers/clk/tegra/
H A Dclk-periph.c41 struct clk_hw *div_hw = &periph->divider.hw;
53 struct clk_hw *div_hw = &periph->divider.hw;
71 struct clk_hw *div_hw = &periph->divider.hw;
122 struct clk_hw *div_hw = &periph->divider.hw;
200 periph->divider.reg = div ? (clk_base + offset) : NULL;
210 periph->divider.hw.clk = div ? clk : NULL;
/linux-master/drivers/cpufreq/
H A Darmada-37xx-cpufreq.c69 * divider, a VDD level, etc...
100 u8 divider[LOAD_LEVEL_NR]; member in struct:armada_37xx_dvfs
109 /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
110 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
111 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
112 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
133 struct regmap *clk_base, u8 *divider)
166 * Set cpu divider based on the pre-computed array in
169 val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
173 /* Set VDD divider whic
132 armada37xx_cpufreq_dvfs_setup(struct regmap *base, struct regmap *clk_base, u8 *divider) argument
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/linux-master/sound/soc/ti/
H A Domap-dmic.c125 int divider = -EINVAL; local
133 divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
138 return divider;
145 divider = 0x4; /* Divider: 16 */
150 divider = 0x5; /* Divider: 5 */
153 divider = 0x0; /* Divider: 8 */
156 divider = 0x2; /* Divider: 10 */
165 divider = 0x3; /* Divider: 8 */
170 divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
178 return divider;
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/linux-master/drivers/comedi/drivers/
H A Ddt3000.c344 unsigned int divider, base, prescale; local
347 /* Don't know if divider==0 works. */
354 divider = DIV_ROUND_CLOSEST(*nanosec, base);
357 divider = (*nanosec) / base;
360 divider = DIV_ROUND_UP(*nanosec, base);
363 if (divider < 65536) {
364 *nanosec = divider * base;
365 return (prescale << 16) | (divider);
371 divider = 65535;
372 *nanosec = divider * bas
457 unsigned int divider; local
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/linux-master/drivers/clk/mvebu/
H A Dap-cpu-clk.c163 int ret, reg, divider = parent_rate / rate; local
175 reg |= (divider << clk->pll_regs->divider_offset);
178 * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
183 reg |= ((divider * clk->pll_regs->divider_ratio) <<
216 int divider = *parent_rate / rate; local
218 divider = min(divider, APN806_MAX_DIVIDER);
220 return *parent_rate / divider;
H A DMakefile18 obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/esw/
H A Dqos.c14 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
15 min_t(u32, max_t(u32, DIV_ROUND_UP(rate, divider), MLX5_MIN_BW_SHARE), limit)
119 /* If vports min rate divider is 0 but their group has bw_share configured, then
127 static u32 esw_qos_calc_bw_share(u32 min_rate, u32 divider, u32 fw_max) argument
129 if (divider)
130 return MLX5_RATE_TO_BW_SHARE(min_rate, divider, fw_max);
140 u32 divider = esw_qos_calculate_min_rate_divider(esw, group, false); local
149 bw_share = esw_qos_calc_bw_share(evport->qos.min_rate, divider, fw_max_bw_share);
164 static int esw_qos_normalize_groups_min_rate(struct mlx5_eswitch *esw, u32 divider, argument
173 bw_share = esw_qos_calc_bw_share(group->min_rate, divider, fw_max_bw_shar
255 u32 previous_min_rate, divider; local
424 u32 divider; local
494 u32 divider; local
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/linux-master/drivers/media/dvb-frontends/
H A Dstv6110.c226 u32 nbsteps, divider, psd2, freq; local
231 divider = (priv->regs[RSTV6110_TUNING2] & 0x0f) << 8;
232 divider += priv->regs[RSTV6110_TUNING1];
239 freq = divider * (priv->mclk / 1000);
252 u32 divider, ref, p, presc, i, result_freq, vco_freq; local
300 divider = (((frequency * 1000) + (ref >> 1)) / ref);
306 /* NDIV_MSB = MSB(divider) */
308 priv->regs[RSTV6110_TUNING2] |= (((divider) >> 8) & 0x0f);
310 /* NDIV_LSB, LSB(divider) */
311 priv->regs[RSTV6110_TUNING1] = (divider
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/linux-master/drivers/clk/berlin/
H A Dberlin2-div.c20 * input pll and divider. The virtual structure as it is used in Marvell
35 * (C) programmable clock divider controlled by <Select[1:n]>
36 * (D) constant div-by-3 clock divider
37 * (E) programmable clock divider bypass controlled by <Switch>
181 u32 divsw, div3sw, divider = 1; local
193 divider = 3;
194 /* divider can be bypassed with DIV_SWITCH == 0 */
196 divider = 1;
197 /* clock divider determined by DIV_SELECT */
203 divider
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H A Dberlin2-avpll.c255 u32 reg, div_av2, div_av3, divider = 1; local
271 divider = reg & VCO_SYNC1_MASK;
281 * HDMI divider start at VCO_CTRL11, bit 7; MSB is enable, lower 2 bit
282 * determine divider.
287 divider *= div_hdmi[reg & 0x3];
290 * AV1 divider start at VCO_CTRL11, bit 28; MSB is enable, lower 2 bit
291 * determine divider.
301 divider *= div_av1[reg & 0x3];
304 * AV2 divider start at VCO_CTRL12, bit 18; each 7 bits wide,
318 divider *
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/linux-master/drivers/clk/xilinx/
H A Dxlnx_vcu.c57 * @pll_post: handle for the VCU PLL post divider
82 * @fbdiv: The integer portion of the feedback divider to the PLL
260 * The output divider of the PLL must be set to 1/2 to meet the
444 struct clk_hw *divider = NULL; local
472 divider = clk_hw_register_divider_parent_hw(dev, name_div, mux,
476 if (IS_ERR(divider)) {
477 err = PTR_ERR(divider);
481 gate = clk_hw_register_gate_parent_hw(dev, name, divider,
492 clk_hw_unregister_divider(divider);
502 struct clk_hw *divider; local
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/linux-master/drivers/clk/ux500/
H A Dclk-prcmu.c29 u8 divider; member in struct:clk_prcmu_clkout
302 return prcmu_config_clkout(clk->clkout_id, clk->source, clk->divider);
322 return (parent_rate / clk->divider);
355 u8 source, u8 divider)
383 clk->divider = divider;
352 clk_reg_prcmu_clkout(const char *name, const char * const *parent_names, int num_parents, u8 source, u8 divider) argument
/linux-master/drivers/clk/
H A Dclk-cdce925.c349 /* Disable clock by setting divider to "0" */
366 unsigned long divider; local
373 divider = DIV_ROUND_CLOSEST(parent_rate, rate);
374 if (divider > 0x7F)
375 divider = 0x7F;
377 return (u16)divider;
427 u16 divider = cdce925_calc_divider(rate, l_parent_rate); local
429 if (l_parent_rate / divider != rate) {
431 divider = cdce925_calc_divider(rate, l_parent_rate);
435 if (divider)
462 unsigned long divider; local
480 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); local
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