Searched refs:L1 (Results 26 - 42 of 42) sorted by relevance
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/linux-master/tools/perf/util/ |
H A D | mem-events.c | 278 "L1", 325 "L1", 626 if (lvl & P(LVL, L1 )) stats->ld_l1hit++; 689 if (lvl & P(LVL, L1 )) stats->st_l1hit++; 692 if (lvl & P(LVL, L1)) stats->st_l1miss++;
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/linux-master/arch/alpha/lib/ |
H A D | ev6-clear_user.S | 20 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1 139 wh64 ($3) # .. .. .. L1 : memory subsystem hint
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H A D | ev6-memcpy.S | 18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1 85 wh64 ($7) # L1 : memory subsystem hint: 64 bytes at
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/linux-master/drivers/pinctrl/aspeed/ |
H A D | pinctrl-aspeed-g4.c | 1489 #define L1 180 macro 1490 SIG_EXPR_LIST_DECL_SINGLE(L1, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); 1491 SIG_EXPR_LIST_DECL_SINGLE(L1, ADC4, ADC4); 1492 PIN_DECL_(L1, SIG_EXPR_LIST_PTR(L1, GPIOW4), SIG_EXPR_LIST_PTR(L1, ADC4)); 1493 FUNC_GROUP_DECL(ADC4, L1); 2047 ASPEED_PINCTRL_PIN(L1), 2500 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA [all...] |
H A D | pinctrl-aspeed-g5.c | 657 #define L1 82 macro 658 SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC); 659 PIN_DECL_1(L1, GPIOK2, SCL6); 665 FUNC_GROUP_DECL(I2C6, L1, N2); 2047 ASPEED_PINCTRL_PIN(L1),
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/linux-master/arch/arm/mach-omap2/ |
H A D | sleep44xx.S | 47 * 1 - CPUx L1 and logic lost: MPUSS CSWR 48 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR 49 * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF 67 * Flush all data from the L1 data cache before disabling 75 mov r1, #0xFF @ clean seucre L1
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/linux-master/arch/arm/mm/ |
H A D | proc-macros.S | 271 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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H A D | cache-v7.S | 31 * the L1; however, the L1 comes out of reset in an undefined state, so 43 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR 190 * working outwards from L1 cache. This is done using Set/Way based cache
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H A D | proc-v7.S | 84 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW 445 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */ 451 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
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/linux-master/drivers/perf/ |
H A D | dwc_pcie_pmu.c | 197 DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1, 0x04),
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/linux-master/arch/x86/events/intel/ |
H A D | ds.c | 82 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */ 179 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); 196 * bit 0: hit L1 data cache 226 * L1 info only valid for following events: 252 *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
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/linux-master/arch/x86/events/amd/ |
H A D | ibs.c | 781 /* L1 Hit */ 783 return L(L1) | LN(L1);
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/linux-master/arch/m68k/ifpsp060/src/ |
H A D | fplsp.S | 6758 # 3.1 R := X + N*L1, # 6759 # where L1 := single-precision(-log2/64). # 6761 # L2 := extended-precision(-log2/64 - L1).# 6762 # Notes: a) The way L1 and L2 are chosen ensures L1+L2 # 6764 # b) N*L1 is exact because N is no longer than 22 bits # 6765 # and L1 is no longer than 24 bits. # 6766 # c) The calculation X+N*L1 is also exact due to # 6767 # cancellation. Thus, R is practically X+N(L1+L2) to full # 6904 # 3.1 R := X + N*L1, # [all...] |
H A D | fpsp.S | 6864 # 3.1 R := X + N*L1, # 6865 # where L1 := single-precision(-log2/64). # 6867 # L2 := extended-precision(-log2/64 - L1).# 6868 # Notes: a) The way L1 and L2 are chosen ensures L1+L2 # 6870 # b) N*L1 is exact because N is no longer than 22 bits # 6871 # and L1 is no longer than 24 bits. # 6872 # c) The calculation X+N*L1 is also exact due to # 6873 # cancellation. Thus, R is practically X+N(L1+L2) to full # 7010 # 3.1 R := X + N*L1, # [all...] |
/linux-master/drivers/pci/pcie/ |
H A D | aspm.c | 3 * Enable PCIe link L0s/L1 state and Clock Power Management 87 * Save L1 substate configuration. The ASPM L0s/L1 configuration 111 * In case BIOS enabled L1.2 when resuming, we need to disable it first 133 /* Make sure L0s/L1 are disabled before updating L1SS config */ 145 * Disable L1.2 on this downstream endpoint device first, followed 155 * in PCI_L1SS_CTL1 must be programmed *before* setting the L1.2 177 /* Restore L0s/L1 if they were enabled */ 195 #define ASPM_STATE_L1 (4) /* L1 state */ 196 #define ASPM_STATE_L1_1 (8) /* ASPM L1 [all...] |
/linux-master/arch/sparc/lib/ |
H A D | M7memcpy.S | 64 * prefetch src data to L2 cache; let HW prefetch move data to L1 cache 82 * align dst on 64 byte boundary; prefetch src data to L1 cache 436 ! Gives existing cache lines time to be moved out of L1/L2/L3 cache.
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/linux-master/arch/sparc/net/ |
H A D | bpf_jit_comp_64.c | 221 [BPF_REG_7] = L1,
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