pci/pcie/aspm.c

3  * Enable PCIe link L0s/L1 state and Clock Power Management
89 	 * Save L1 substate configuration. The ASPM L0s/L1 configuration
113 	 * In case BIOS enabled L1.2 when resuming, we need to disable it first
135 	/* Make sure L0s/L1 are disabled before updating L1SS config */
147 	 * Disable L1.2 on this downstream endpoint device first, followed
157 	 * in PCI_L1SS_CTL1 must be programmed *before* setting the L1.2
179 	/* Restore L0s/L1 if they were enabled */
256  * The L1 PM substate capability is only implemented in function 0 in a
276 		/* Enable ASPM L0s/L1 */
473 /* Convert L1 latency encoding to ns */
483 /* Convert L1 acceptable latency encoding to ns */
507  * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1
508  * register.  Ports enter L1.2 when the most recent LTR value is greater
510  * don't enter L1.2 too aggressively.
565 	/* Calculate endpoint L1 acceptable latency */
592 		 * Check L1 latency.
594 		 * more microsecond for L1. Spec doesn't mention L0s.
596 		 * The exit latencies for L1 substates are not advertised
598 		 * to determine max latencies introduced by enabling L1
600 		 * a L1 substate exit latency check.  We assume that the
601 		 * L1 exit latencies advertised by a device include L1
614 /* Calculate L1.2 PM substate timing parameters */
649 	 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
654 	 * Table 5-11.  T(POWER_OFF) is at most 2us and T(L1.2) is at
663 	/* Some broken devices only support dword access to L1 SS */
673 	/* Disable L1.2 while updating.  See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
723 	/* Setup L1 substate */
736 	 * to this device, we can't use ASPM L1.2 because it relies on the
799 	 * clock configuration.  L0s & L1 exit latencies in the otherwise
823 	/* Setup L1 state */
848 /* Configure the ASPM L1 substates */
858 	 * - When enabling L1.x, enable bit at parent first, then at child
859 	 * - When disabling L1.x, disable bit at child first, then at parent
860 	 * - When enabling ASPM L1.x, need to disable L1
862 	 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
869 	/* Disable all L1 substates */
875 	 * If needed, disable L1, and it gets enabled later
917 	/* Can't enable any substates if L1 is not enabled */
945 	 * same setting for ASPM. Enabling ASPM L1 should be done in
947 	 * versa for disabling ASPM L1. Spec doesn't mention L0S.
1330 	/* L1 PM substates require L1 */
1341 	/* L1 PM substates require L1 */
1561 		/* need to enable L1 for substates */
1589 ASPM_ATTR(l1_aspm, L1)