Searched refs:sr (Results 26 - 50 of 334) sorted by path

1234567891011>>

/linux-master/arch/sh/kernel/
H A Drelocate_kernel.S39 stc.l sr, @-r15
45 stc sr, r8
47 ldc r8, sr
60 stc sr, r8
62 ldc r8, sr
92 stc sr, r8
94 ldc r8, sr
106 stc sr, r8
108 ldc r8, sr
121 stc sr, r
[all...]
/linux-master/arch/xtensa/variants/csp/include/variant/
H A Dtie.h90 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
92 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
94 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
116 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
117 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,3
[all...]
/linux-master/arch/xtensa/variants/dc232b/include/variant/
H A Dtie.h71 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
73 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
75 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
97 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
98 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
99 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
100 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,1
[all...]
/linux-master/arch/xtensa/variants/dc233c/include/variant/
H A Dtie.h90 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
92 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
94 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
116 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
117 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,1
[all...]
/linux-master/arch/xtensa/variants/de212/include/variant/
H A Dtie.h67 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
69 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
71 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
90 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
91 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
92 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
93 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
95 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,3
[all...]
/linux-master/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dtie.h93 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
95 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
97 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
122 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
123 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,3
[all...]
/linux-master/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dtie.h93 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
95 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
97 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
122 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
123 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,
[all...]
/linux-master/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dtie.h70 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
72 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
74 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
93 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dconn.c90 info->sr = (nvbios_rd08(bios, data + 0x03) & 0x08) >> 3;
/linux-master/drivers/ipack/devices/
H A Dscc2698.h24 u8 d1, sr; /* Status register */ member in struct:scc2698_channel::__anon343
/linux-master/drivers/macintosh/
H A Dwindfarm.h100 int (*get_value)(struct wf_sensor *sr, s32 *val);
101 void (*release)(struct wf_sensor *sr);
115 extern int wf_register_sensor(struct wf_sensor *sr);
116 extern void wf_unregister_sensor(struct wf_sensor *sr);
117 extern int wf_get_sensor(struct wf_sensor *sr);
118 extern void wf_put_sensor(struct wf_sensor *sr);
120 static inline int wf_sensor_get(struct wf_sensor *sr, s32 *val) argument
122 return sr->ops->get_value(sr, val);
/linux-master/drivers/net/wan/
H A Dwanxlfw.S255 movew #0x2700, %sr // disable IRQs again
607 movew %sr, -(%sp)
613 movew #0x2700, %sr // disable interrupts again
618 movew %sr, -(%sp)
624 movew #0x2700, %sr // disable interrupts again
628 movew (%sp)+, %sr
/linux-master/drivers/sh/intc/
H A Dhandle.c261 struct intc_sense_reg *sr = desc->hw.sense_regs; local
264 for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
265 sr = desc->hw.sense_regs + i;
267 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
268 if (sr->enum_ids[j] != enum_id)
272 fn += (sr->reg_width >> 3) - 1;
274 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
276 bit = sr->reg_width - ((j + 1) * sr
[all...]
/linux-master/include/misc/
H A Dcxllib.h101 u64 sr; member in struct:cxllib_pe_attributes
/linux-master/lib/reed_solomon/
H A Dreed_solomon.c73 int i, j, sr, root, iprim; local
107 sr = 1;
109 rs->index_of[sr] = i;
110 rs->alpha_to[i] = sr;
111 sr <<= 1;
112 if (sr & (1 << symsize))
113 sr ^= gfpoly;
114 sr &= rs->nn;
117 sr = gffunc(0);
119 rs->index_of[sr]
[all...]
/linux-master/sound/pci/au88x0/
H A Dau88x0_synth.c358 static void vortex_wt_SetFrequency(vortex_t * vortex, int wt, unsigned int sr)
364 eax = ((sr << 0xf) * 0x57619F1) & 0xffffffff;
365 edx = (((sr << 0xf) * 0x57619F1)) >> 0x20;
H A Dau88x0_xtalk.h39 static void vortex_XtalkHw_SetSampleRate(vortex_t * vortex, u32 sr);
/linux-master/sound/soc/fsl/
H A Dfsl_dma.h13 __be32 sr; /* Status register */ member in struct:ccsr_dma::ccsr_dma_channel
/linux-master/arch/arc/include/asm/
H A Ddsp-impl.h23 sr r5, [ARC_AUX_DSP_CTRL]
36 sr r10, [ARC_AUX_DSP_CTRL]
54 sr r10, [ARC_AUX_DSP_CTRL]
H A Dentry-arcv2.h202 sr r10, [AUX_USER_SP]
219 sr r10, [lp_end]
220 sr r11, [lp_start]
263 sr r10, [erbta]
266 sr r10, [eret]
267 sr r11, [erstatus]
H A Dentry-compact.h54 sr r9, [\aux]
198 sr r9, [erstatus]
200 sr r9, [eret]
H A Dmmu-arcv2.h98 sr \reg, [ARC_REG_PID]
/linux-master/arch/arc/kernel/
H A Dentry-arcv2.S211 sr r11, [AUX_IRQ_ACT]
246 sr r11, [AUX_IRQ_ACT]
H A Dentry-compact.S189 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
214 sr r3, [status32_l2]
244 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
H A Dhead.S23 sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
34 sr r5, [ARC_REG_IC_CTRL]
46 sr r5, [ARC_REG_DC_CTRL]
67 sr r5, [ARC_REG_LPB_CTRL]
76 sr r6, [ARC_REG_AUX_ICCM]
80 sr r6, [ARC_REG_AUX_DCCM]

Completed in 594 milliseconds

1234567891011>>