History log of /linux-master/arch/arc/include/asm/entry-arcv2.h
Revision Date Author Comments
# 9de7fc30 21-May-2020 Vineet Gupta <vgupta@kernel.org>

ARC: entry: SAVE_ABI_CALLEE_REG: ISA/ABI specific helper

And for ARcompact variant replace the PUSH/POP macros with gas provided
push/pop pseudo-instructions

This allows ISA specific implementation

e.g. Current ARCv2 PUSH/POP could be replaced with STD/LDL to save 2
registers at a time (w/o bothering with SP update each time) or
perhaps use ENTER_S/LEAVE_S to reduce code size

For ARCv3 ABI changed so callee regs are now r14-r26 (vs. r13-r25)
thus would need a different implementation.

Signed-off-by: Vineet Gupta <vgupta@kernel.org>


# d4624bf6 22-May-2020 Vineet Gupta <vgupta@kernel.org>

ARCv2: entry: rearrange pt_regs slightly

Instead of r26,fp,sp,r12,r30 order as fp,r30,r12,r26,sp

- keeps SP at well known position (right abive hardware autosave)
- r26,r12 saved specifically for ARCv2 (and not in ARCv3) kept
closer for easy ifdef'ry later

Signed-off-by: Vineet Gupta <vgupta@kernel.org>


# 656f18ad 18-Jun-2020 Vineet Gupta <vgupta@kernel.org>

ARC: entry: replace 8 byte ADD.ne with 4 byte ADD2.ne

ARCv2 current
------------
000007e0 <EV_Trap>:
7e0: 2482 3c01 sub sp,sp,112
7e4: 1c28 3006 std r0r1,[sp,40]
7e8: 1c30 3086 std r2r3,[sp,48]
7ec: 1c38 3106 std r4r5,[sp,56]
7f0: 1c40 3186 std r6r7,[sp,64]
7f4: 1c48 3206 std r8r9,[sp,72]
7f8: 1c50 3286 std r10r11,[sp,80]
7fc: 1c58 37c0 st blink,[sp,88]
800: 1c0c 36c0 st fp,[sp,12]
804: 1c18 3680 st gp,[sp,24]
808: 1c10 3780 st r30,[sp,16]
80c: 1c14 3300 st r12,[sp,20]
810: 226a 1340 lr r10,[aux_user_sp]
814: 22ca 1702 mov.ne r10,sp
818: 22c0 1f82 0000 0070 add.ne r10,r10,0x70
^^^^^^^^^
With fix
--------
000007b4 <EV_Trap>:
7b4: 2482 3c01 sub sp,sp,112
7b8: 1c28 3006 std r0r1,[sp,40]
7bc: 1c30 3086 std r2r3,[sp,48]
7c0: 1c38 3106 std r4r5,[sp,56]
7c4: 1c40 3186 std r6r7,[sp,64]
7c8: 1c48 3206 std r8r9,[sp,72]
7cc: 1c50 3286 std r10r11,[sp,80]
7d0: 1c58 37c0 st blink,[sp,88]
7d4: 1c0c 36c0 st fp,[sp,12]
7d8: 1c18 3680 st gp,[sp,24]
7dc: 1c10 3780 st r30,[sp,16]
7e0: 1c14 3300 st r12,[sp,20]
7e4: 226a 1340 lr r10,[aux_user_sp]
7e8: 22ca 1702 mov.ne r10,sp
7ec: 22d5 1722 add2.ne r10,r10,0x1c

Signed-off-by: Vineet Gupta <vgupta@kernel.org>


# dfb12071 17-Jun-2020 Vineet Gupta <vgupta@kernel.org>

ARC: entry: replace 8 byte OR with 4 byte BSET

FAKE_RET_FROM_EXCEPTION drops down to pure kernel mode. It currently has
an 8 byte instruction which can be replaced with 4 byte BSET

This is applicable to both ARCv2 and ARCv3 entr code.

ARCv2 current
------------
00000804 <EV_Trap>:
...
874: 216a 1280 lr r9,[status32]
878: 2146 1809 bic r9,r9,0x20
87c: 2105 1f89 8000 0000 or r9,r9,0x80000000
^^^^^^^^^
884: 2029 8240 kflag r9

ARCv2 after
----------
000007e0 <EV_Trap>:
...
850: 216a 1280 lr r9,[status32]
854: 2150 1149 bclr r9,r9,0x5
858: 214f 17c9 bset r9,r9,0x1f
85c: 2029 8240 kflag r9

Signed-off-by: Vineet Gupta <vgupta@kernel.org>


# 13347c10 20-May-2020 Vineet Gupta <vgupta@kernel.org>

ARC: entry: Add more common chores to EXCEPTION_PROLOGUE

THe high level structure of most ARC exception handlers is
1. save regfile with EXCEPTION_PROLOGUE
2. setup r0: EFA (not part of pt_regs)
3. setup r1: pointer to pt_regs (SP)
4. drop down to pure kernel mode (from exception)
5. call the Linux "C" handler

Remove the boiler plate code by moving #2, #3, #4 into #1.

The exceptions to most exceptions are syscall Trap and Machine check
which don't do some of above for various reasons, so call a newly
introduced variant EXCEPTION_PROLOGUE_KEEP_AE (same as original
EXCEPTION_PROLOGUE)

Tested-by: Pavel Kozlov <Pavel.Kozlov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@kernel.org>


# c505b0da 19-May-2020 Vineet Gupta <vgupta@kernel.org>

ARC: entry: rework (non-functional)

- comments update
- rename syscall_trace_entry
- use PT_xxx in entry code

Signed-off-by: Vineet Gupta <vgupta@kernel.org>


# cfca4b5a 12-May-2020 Vineet Gupta <vgupta@kernel.org>

ARC: entry: use gp to cache task pointer (vs. r25)

The motivation is eventual ABI considerations for ARCv3 but even without
it this change us worthwhile as diffstat reduces 100 net lines

r25 is a callee saved register, normally not saved by entry code in
pt_regs. However because of its usage in CONFIG_ARC_CURR_IN_REG it needs
to be. This in turn requires a whole bunch of special casing when we
need to access r25. Then there is distinction between user mode r25 vs.
kernel mode r25 - hence distinct SAVE_CALLEE_SAVED_{USER,KERNEL}

Instead use gp which is a scratch register and thus saved already in entry
code. This cleans things up significantly and much nocer on eyes:

- SAVE_CALLEE_SAVED_{USER,KERNEL} are now exactly same
- no special user_r25 slot in pt_reggs

Note that typical global asm registers are callee-saved (r25), but gp is
not callee-saved thus needs additional -ffixed-<reg> toggle

Signed-off-by: Vineet Gupta <vgupta@kernel.org>


# 49b41356 10-Apr-2020 Vineet Gupta <vgupta@synopsys.com>

ARC: entry: comment

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# 7321e2ea 05-Mar-2020 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

ARC: add support for DSP-enabled userspace applications

To be able to run DSP-enabled userspace applications we need to
save and restore following DSP-related registers:
At IRQ/exception entry/exit:
* DSP_CTRL (save it and reset to value suitable for kernel)
* ACC0_LO, ACC0_HI (we already save them as r58, r59 pair)
At context switch:
* ACC0_GLO, ACC0_GHI
* DSP_BFLY0, DSP_FFT_CTRL

Reviewed-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# 4827d0cf 05-Mar-2020 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

ARC: handle DSP presence in HW

When DSP extensions are present, some of the regular integer instructions
such as DIV, MACD etc are executed in the DSP unit with semantics alterable
by flags in DSP_CTRL aux register. This register is writable by userspace
and thus can potentially affect corresponding instructions in kernel code,
intentionally or otherwise. So safegaurd kernel by effectively disabling
DSP_CTRL upon bootup and every entry to kernel.

Do note that for this config we simply zero out the DSP_CTRL reg assuming
userspace doesn't really care about DSP. The next patch caters to the DSP
aware userspace where this reg is saved/restored upon kernel entry/exit.

Reviewed-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# 7ecc6c1d 27-Dec-2019 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

ARC: pt_regs: remove hardcoded registers offset

Replace hardcoded registers offset numbers by calculated via
offsetof.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# 97abfd5d 16-Jul-2019 Alexey Brodkin <Alexey.Brodkin@synopsys.com>

ARCv2: entry: early return from exception need not clear U & DE bits

Exception handlers call FAKE_RET_FROM_EXCPN to
- clear AE bit: drop down from exception active to pure kernel mode
allowing further excptions
- set IE bit: re-enable interrupts

It additionally also clears U bit (user mode) and DE bit (delay slot
execution) which is redundant as hardware does that already on any taken
exception. Morevoer the current software clearing is bogus anyways as
the KFLAG instruction being used for purpose can't possibly write those
bits anyways.

So don't pretend to clear them.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[vgupta: rewrote changelog]


# 68e5c6f0 15-May-2019 Vineet Gupta <vgupta@synopsys.com>

ARC: entry: EV_Trap expects r10 (vs. r9) to have exception cause

avoids 1 MOV instruction in light of double load/store code

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# a4880801 15-May-2019 Vineet Gupta <vgupta@synopsys.com>

ARCv2: entry: rewrite to enable use of double load/stores LDD/STD

- the motivation was to be remove blatent copy-paste due to hasty support
of CONFIG_ARC_IRQ_NO_AUTOSAVE support

- but with refactoring we could use LDD/STD to greatly optimize the code

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# ab854bfc 10-May-2019 Vineet Gupta <vgupta@synopsys.com>

ARCv2: entry: avoid a branch

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# 23c0cbd0 09-Apr-2019 Vineet Gupta <vgupta@synopsys.com>

ARCv2: entry: push out the Z flag unclobber from common EXCEPTION_PROLOGUE

Upon a taken interrupt/exception from User mode, HS hardware auto sets Z flag.
This helps shave a few instructions from EXCEPTION_PROLOGUE by eliding
re-reading ERSTATUS and some bit fiddling.

However TLB Miss Exception handler can clobber the CPU flags and still end
up in EXCEPTION_PROLOGUE in the slow path handling TLB handling case:

EV_TLBMissD
do_slow_path_pf
EV_TLBProtV (aliased to call_do_page_fault)
EXCEPTION_PROLOGUE

As a result, EXCEPTION_PROLOGUE need to "unclobber" the Z flag which this
patch changes. It is now pushed out to TLB Miss Exception handler.
The reasons beings:

- The flag restoration is only needed for slowpath TLB Miss Exception
handling, but currently being in EXCEPTION_PROLOGUE penalizes all
exceptions such as ProtV and syscall Trap, where Z flag is already
as expected.

- Pushing unclobber out to where it was clobbered is much cleaner and
also serves to document the fact.

- Makes EXCEPTION_PROLGUE similar to INTERRUPT_PROLOGUE so easier to
refactor the common parts which is what this series aims to do

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# 45869eb0 09-Apr-2019 Vineet Gupta <vgupta@synopsys.com>

ARCv2: entry: comments about hardware auto-save on taken interrupts

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# e494239a 06-Jun-2018 Vineet Gupta <vgupta@synopsys.com>

ARCv2: support manual regfile save on interrupts

There's a hardware bug which affects the HSDK platform, triggered by
micro-ops for auto-saving regfile on taken interrupt. The workaround is
to inhibit autosave.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# a3142792 18-Jan-2018 Alexey Brodkin <abrodkin@synopsys.com>

ARCv2: Don't pretend we may set L-bit in STATUS32 with kflag instruction

As per PRM "kflag" instruction doesn't change state of
L-flag ("Zero-Overhead loop disabled") in STATUS32 register
so let's not act as if we can affect this bit.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# b2441318 01-Nov-2017 Greg Kroah-Hartman <gregkh@linuxfoundation.org>

License cleanup: add SPDX GPL-2.0 license identifier to files with no license

Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.

By default all files without license information are under the default
license of the kernel, which is GPL version 2.

Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.

This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.

How this work was done:

Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,

Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.

The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.

The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.

Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).

All documentation files were explicitly excluded.

The following heuristics were used to determine which SPDX license
identifiers to apply.

- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.

For non */uapi/* files that summary was:

SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139

and resulted in the first patch in this series.

If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:

SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930

and resulted in the second patch in this series.

- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:

SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1

and that resulted in the third patch in this series.

- when the two scanners agreed on the detected license(s), that became
the concluded license(s).

- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.

- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).

- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.

- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.

In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.

Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.

Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.

In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.

Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct

This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.

These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.

Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>


# 3d5e8012 20-Apr-2017 Vineet Gupta <vgupta@synopsys.com>

ARCv2: entry: save Accumulator register pair (r58:59) if present

Accumulator is present in configs with FPU and/or DSP MPY (mpy > 6)

Instead of doing this in pt_regs (and thus every kernel entry/exit),
this could have been done in context switch (and for user task only) as
currently kernel doesn't clobber these registers for its own accord.
However we will soon start using 64-bit multiply instructions for kernel
which can clobber these. Also gcc folks also plan to start using these
as GPRs, hence better to always save/restore them

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# ecd43afd 08-Jan-2017 Vineet Gupta <vgupta@synopsys.com>

ARCv2: save r30 on kernel entry as gcc uses it for code-gen

This is not exposed to userspace debugers yet, which can be done
independently as a seperate patch !

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>


# 1f6ccfff 13-May-2013 Vineet Gupta <vgupta@synopsys.com>

ARCv2: Support for ARCv2 ISA and HS38x cores

The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>