1220791Smdf/* SPDX-License-Identifier: GPL-2.0-only */ 2220791Smdf/* 3220791Smdf * scc2698.h 4220791Smdf * 5220791Smdf * driver for the IPOCTAL boards 6220791Smdf * 7220791Smdf * Copyright (C) 2009-2012 CERN (www.cern.ch) 8220791Smdf * Author: Nicolas Serafini, EIC2 SA 9220791Smdf * Author: Samuel Iglesias Gonsalvez <siglesias@igalia.com> 10220791Smdf */ 11220791Smdf 12220791Smdf#ifndef SCC2698_H_ 13220791Smdf#define SCC2698_H_ 14220791Smdf 15220791Smdf/* 16220791Smdf * union scc2698_channel - Channel access to scc2698 IO 17220791Smdf * 18220791Smdf * dn value are only spacer. 19220791Smdf * 20220791Smdf */ 21220791Smdfunion scc2698_channel { 22220791Smdf struct { 23220791Smdf u8 d0, mr; /* Mode register 1/2*/ 24220791Smdf u8 d1, sr; /* Status register */ 25220791Smdf u8 d2, r1; /* reserved */ 26220791Smdf u8 d3, rhr; /* Receive holding register (R) */ 27220791Smdf u8 junk[8]; /* other crap for block control */ 28220791Smdf } __packed r; /* Read access */ 29220791Smdf struct { 30220791Smdf u8 d0, mr; /* Mode register 1/2 */ 31261280Spluknet u8 d1, csr; /* Clock select register */ 32220791Smdf u8 d2, cr; /* Command register */ 33220791Smdf u8 d3, thr; /* Transmit holding register */ 34220791Smdf u8 junk[8]; /* other crap for block control */ 35220791Smdf } __packed w; /* Write access */ 36220791Smdf}; 37220791Smdf 38220791Smdf/* 39220791Smdf * union scc2698_block - Block access to scc2698 IO 40220791Smdf * 41220791Smdf * The scc2698 contain 4 block. 42220791Smdf * Each block containt two channel a and b. 43220791Smdf * dn value are only spacer. 44220791Smdf * 45220791Smdf */ 46220791Smdfunion scc2698_block { 47220791Smdf struct { 48220791Smdf u8 d0, mra; /* Mode register 1/2 (a) */ 49220791Smdf u8 d1, sra; /* Status register (a) */ 50220791Smdf u8 d2, r1; /* reserved */ 51232157Sgjb u8 d3, rhra; /* Receive holding register (a) */ 52220791Smdf u8 d4, ipcr; /* Input port change register of block */ 53220791Smdf u8 d5, isr; /* Interrupt status register of block */ 54220791Smdf u8 d6, ctur; /* Counter timer upper register of block */ 55220791Smdf u8 d7, ctlr; /* Counter timer lower register of block */ 56220791Smdf u8 d8, mrb; /* Mode register 1/2 (b) */ 57220791Smdf u8 d9, srb; /* Status register (b) */ 58220791Smdf u8 da, r2; /* reserved */ 59220791Smdf u8 db, rhrb; /* Receive holding register (b) */ 60220791Smdf u8 dc, r3; /* reserved */ 61220791Smdf u8 dd, ip; /* Input port register of block */ 62220791Smdf u8 de, ctg; /* Start counter timer of block */ 63220791Smdf u8 df, cts; /* Stop counter timer of block */ 64220791Smdf } __packed r; /* Read access */ 65220791Smdf struct { 66220791Smdf u8 d0, mra; /* Mode register 1/2 (a) */ 67220791Smdf u8 d1, csra; /* Clock select register (a) */ 68220791Smdf u8 d2, cra; /* Command register (a) */ 69220791Smdf u8 d3, thra; /* Transmit holding register (a) */ 70220791Smdf u8 d4, acr; /* Auxiliary control register of block */ 71220791Smdf u8 d5, imr; /* Interrupt mask register of block */ 72220791Smdf u8 d6, ctu; /* Counter timer upper register of block */ 73220791Smdf u8 d7, ctl; /* Counter timer lower register of block */ 74220791Smdf u8 d8, mrb; /* Mode register 1/2 (b) */ 75220791Smdf u8 d9, csrb; /* Clock select register (a) */ 76220791Smdf u8 da, crb; /* Command register (b) */ 77220791Smdf u8 db, thrb; /* Transmit holding register (b) */ 78220791Smdf u8 dc, r1; /* reserved */ 79220791Smdf u8 dd, opcr; /* Output port configuration register of block */ 80220791Smdf u8 de, r2; /* reserved */ 81220791Smdf u8 df, r3; /* reserved */ 82220791Smdf } __packed w; /* Write access */ 83220791Smdf}; 84220791Smdf 85220791Smdf#define MR1_CHRL_5_BITS (0x0 << 0) 86261560Skib#define MR1_CHRL_6_BITS (0x1 << 0) 87261560Skib#define MR1_CHRL_7_BITS (0x2 << 0) 88220791Smdf#define MR1_CHRL_8_BITS (0x3 << 0) 89220791Smdf#define MR1_PARITY_EVEN (0x1 << 2) 90220791Smdf#define MR1_PARITY_ODD (0x0 << 2) 91220791Smdf#define MR1_PARITY_ON (0x0 << 3) 92220791Smdf#define MR1_PARITY_FORCE (0x1 << 3) 93220791Smdf#define MR1_PARITY_OFF (0x2 << 3) 94220791Smdf#define MR1_PARITY_SPECIAL (0x3 << 3) 95220791Smdf#define MR1_ERROR_CHAR (0x0 << 5) 96220791Smdf#define MR1_ERROR_BLOCK (0x1 << 5) 97220791Smdf#define MR1_RxINT_RxRDY (0x0 << 6) 98220791Smdf#define MR1_RxINT_FFULL (0x1 << 6) 99220791Smdf#define MR1_RxRTS_CONTROL_ON (0x1 << 7) 100220791Smdf#define MR1_RxRTS_CONTROL_OFF (0x0 << 7) 101220791Smdf 102220791Smdf#define MR2_STOP_BITS_LENGTH_1 (0x7 << 0) 103220791Smdf#define MR2_STOP_BITS_LENGTH_2 (0xF << 0) 104220791Smdf#define MR2_CTS_ENABLE_TX_ON (0x1 << 4) 105220791Smdf#define MR2_CTS_ENABLE_TX_OFF (0x0 << 4) 106220791Smdf#define MR2_TxRTS_CONTROL_ON (0x1 << 5) 107220791Smdf#define MR2_TxRTS_CONTROL_OFF (0x0 << 5) 108220791Smdf#define MR2_CH_MODE_NORMAL (0x0 << 6) 109261280Spluknet#define MR2_CH_MODE_ECHO (0x1 << 6) 110220791Smdf#define MR2_CH_MODE_LOCAL (0x2 << 6) 111220791Smdf#define MR2_CH_MODE_REMOTE (0x3 << 6) 112220791Smdf 113220791Smdf#define CR_ENABLE_RX (0x1 << 0) 114220791Smdf#define CR_DISABLE_RX (0x1 << 1) 115220791Smdf#define CR_ENABLE_TX (0x1 << 2) 116220791Smdf#define CR_DISABLE_TX (0x1 << 3) 117220791Smdf#define CR_CMD_RESET_MR (0x1 << 4) 118220791Smdf#define CR_CMD_RESET_RX (0x2 << 4) 119220791Smdf#define CR_CMD_RESET_TX (0x3 << 4) 120220791Smdf#define CR_CMD_RESET_ERR_STATUS (0x4 << 4) 121220791Smdf#define CR_CMD_RESET_BREAK_CHANGE (0x5 << 4) 122220791Smdf#define CR_CMD_START_BREAK (0x6 << 4) 123220791Smdf#define CR_CMD_STOP_BREAK (0x7 << 4) 124220791Smdf#define CR_CMD_ASSERT_RTSN (0x8 << 4) 125220791Smdf#define CR_CMD_NEGATE_RTSN (0x9 << 4) 126220791Smdf#define CR_CMD_SET_TIMEOUT_MODE (0xA << 4) 127220791Smdf#define CR_CMD_DISABLE_TIMEOUT_MODE (0xC << 4) 128220791Smdf 129220791Smdf#define SR_RX_READY (0x1 << 0) 130220791Smdf#define SR_FIFO_FULL (0x1 << 1) 131220791Smdf#define SR_TX_READY (0x1 << 2) 132220791Smdf#define SR_TX_EMPTY (0x1 << 3) 133220791Smdf#define SR_OVERRUN_ERROR (0x1 << 4) 134220791Smdf#define SR_PARITY_ERROR (0x1 << 5) 135220791Smdf#define SR_FRAMING_ERROR (0x1 << 6) 136220791Smdf#define SR_RECEIVED_BREAK (0x1 << 7) 137220791Smdf 138220791Smdf#define SR_ERROR (0xF0) 139220791Smdf 140220791Smdf#define ACR_DELTA_IP0_IRQ_EN (0x1 << 0) 141220791Smdf#define ACR_DELTA_IP1_IRQ_EN (0x1 << 1) 142220791Smdf#define ACR_DELTA_IP2_IRQ_EN (0x1 << 2) 143220791Smdf#define ACR_DELTA_IP3_IRQ_EN (0x1 << 3) 144220791Smdf#define ACR_CT_Mask (0x7 << 4) 145#define ACR_CExt (0x0 << 4) 146#define ACR_CTxCA (0x1 << 4) 147#define ACR_CTxCB (0x2 << 4) 148#define ACR_CClk16 (0x3 << 4) 149#define ACR_TExt (0x4 << 4) 150#define ACR_TExt16 (0x5 << 4) 151#define ACR_TClk (0x6 << 4) 152#define ACR_TClk16 (0x7 << 4) 153#define ACR_BRG_SET1 (0x0 << 7) 154#define ACR_BRG_SET2 (0x1 << 7) 155 156#define TX_CLK_75 (0x0 << 0) 157#define TX_CLK_110 (0x1 << 0) 158#define TX_CLK_38400 (0x2 << 0) 159#define TX_CLK_150 (0x3 << 0) 160#define TX_CLK_300 (0x4 << 0) 161#define TX_CLK_600 (0x5 << 0) 162#define TX_CLK_1200 (0x6 << 0) 163#define TX_CLK_2000 (0x7 << 0) 164#define TX_CLK_2400 (0x8 << 0) 165#define TX_CLK_4800 (0x9 << 0) 166#define TX_CLK_1800 (0xA << 0) 167#define TX_CLK_9600 (0xB << 0) 168#define TX_CLK_19200 (0xC << 0) 169#define RX_CLK_75 (0x0 << 4) 170#define RX_CLK_110 (0x1 << 4) 171#define RX_CLK_38400 (0x2 << 4) 172#define RX_CLK_150 (0x3 << 4) 173#define RX_CLK_300 (0x4 << 4) 174#define RX_CLK_600 (0x5 << 4) 175#define RX_CLK_1200 (0x6 << 4) 176#define RX_CLK_2000 (0x7 << 4) 177#define RX_CLK_2400 (0x8 << 4) 178#define RX_CLK_4800 (0x9 << 4) 179#define RX_CLK_1800 (0xA << 4) 180#define RX_CLK_9600 (0xB << 4) 181#define RX_CLK_19200 (0xC << 4) 182 183#define OPCR_MPOa_RTSN (0x0 << 0) 184#define OPCR_MPOa_C_TO (0x1 << 0) 185#define OPCR_MPOa_TxC1X (0x2 << 0) 186#define OPCR_MPOa_TxC16X (0x3 << 0) 187#define OPCR_MPOa_RxC1X (0x4 << 0) 188#define OPCR_MPOa_RxC16X (0x5 << 0) 189#define OPCR_MPOa_TxRDY (0x6 << 0) 190#define OPCR_MPOa_RxRDY_FF (0x7 << 0) 191 192#define OPCR_MPOb_RTSN (0x0 << 4) 193#define OPCR_MPOb_C_TO (0x1 << 4) 194#define OPCR_MPOb_TxC1X (0x2 << 4) 195#define OPCR_MPOb_TxC16X (0x3 << 4) 196#define OPCR_MPOb_RxC1X (0x4 << 4) 197#define OPCR_MPOb_RxC16X (0x5 << 4) 198#define OPCR_MPOb_TxRDY (0x6 << 4) 199#define OPCR_MPOb_RxRDY_FF (0x7 << 4) 200 201#define OPCR_MPP_INPUT (0x0 << 7) 202#define OPCR_MPP_OUTPUT (0x1 << 7) 203 204#define IMR_TxRDY_A (0x1 << 0) 205#define IMR_RxRDY_FFULL_A (0x1 << 1) 206#define IMR_DELTA_BREAK_A (0x1 << 2) 207#define IMR_COUNTER_READY (0x1 << 3) 208#define IMR_TxRDY_B (0x1 << 4) 209#define IMR_RxRDY_FFULL_B (0x1 << 5) 210#define IMR_DELTA_BREAK_B (0x1 << 6) 211#define IMR_INPUT_PORT_CHANGE (0x1 << 7) 212 213#define ISR_TxRDY_A (0x1 << 0) 214#define ISR_RxRDY_FFULL_A (0x1 << 1) 215#define ISR_DELTA_BREAK_A (0x1 << 2) 216#define ISR_COUNTER_READY (0x1 << 3) 217#define ISR_TxRDY_B (0x1 << 4) 218#define ISR_RxRDY_FFULL_B (0x1 << 5) 219#define ISR_DELTA_BREAK_B (0x1 << 6) 220#define ISR_INPUT_PORT_CHANGE (0x1 << 7) 221 222#define ACK_INT_REQ0 0 223#define ACK_INT_REQ1 2 224 225#endif /* SCC2698_H_ */ 226