1139749Simp/* SPDX-License-Identifier: GPL-2.0-or-later */ 276479Swpaul/* 376479Swpaul * Copyright 2017 IBM Corp. 476479Swpaul */ 576479Swpaul 676479Swpaul#ifndef _MISC_CXLLIB_H 776479Swpaul#define _MISC_CXLLIB_H 876479Swpaul 976479Swpaul#include <linux/pci.h> 1076479Swpaul#include <asm/reg.h> 1176479Swpaul 1276479Swpaul/* 1376479Swpaul * cxl driver exports a in-kernel 'library' API which can be called by 1476479Swpaul * other drivers to help interacting with an IBM XSL. 1576479Swpaul */ 1676479Swpaul 1776479Swpaul/* 1876479Swpaul * tells whether capi is supported on the PCIe slot where the 1976479Swpaul * device is seated 2076479Swpaul * 2176479Swpaul * Input: 2276479Swpaul * dev: device whose slot needs to be checked 2376479Swpaul * flags: 0 for the time being 2476479Swpaul */ 2576479Swpaulbool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags); 2676479Swpaul 2776479Swpaul 2876479Swpaul/* 2976479Swpaul * Returns the configuration parameters to be used by the XSL or device 3076479Swpaul * 3176479Swpaul * Input: 3276479Swpaul * dev: device, used to find PHB 3376479Swpaul * Output: 34119418Sobrien * struct cxllib_xsl_config: 35119418Sobrien * version 36119418Sobrien * capi BAR address, i.e. 0x2000000000000-0x2FFFFFFFFFFFF 3776479Swpaul * capi BAR size 3876479Swpaul * data send control (XSL_DSNCTL) 3976479Swpaul * dummy read address (XSL_DRA) 4076479Swpaul */ 4176479Swpaul#define CXL_XSL_CONFIG_VERSION1 1 4276479Swpaulstruct cxllib_xsl_config { 4376479Swpaul u32 version; /* format version for register encoding */ 4476479Swpaul u32 log_bar_size;/* log size of the capi_window */ 4576479Swpaul u64 bar_addr; /* address of the start of capi window */ 4676479Swpaul u64 dsnctl; /* matches definition of XSL_DSNCTL */ 4776479Swpaul u64 dra; /* real address that can be used for dummy read */ 4876479Swpaul}; 4976479Swpaul 5076479Swpaulint cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg); 5176479Swpaul 5276479Swpaul 5376479Swpaul/* 5476479Swpaul * Activate capi for the pci host bridge associated with the device. 5576479Swpaul * Can be extended to deactivate once we know how to do it. 5676479Swpaul * Device must be ready to accept messages from the CAPP unit and 5776479Swpaul * respond accordingly (TLB invalidates, ...) 5876479Swpaul * 5976479Swpaul * PHB is switched to capi mode through calls to skiboot. 6076479Swpaul * CAPP snooping is activated 6176479Swpaul * 6276479Swpaul * Input: 6376479Swpaul * dev: device whose PHB should switch mode 6476479Swpaul * mode: mode to switch to i.e. CAPI or PCI 6576479Swpaul * flags: options related to the mode 6676479Swpaul */ 6776479Swpaulenum cxllib_mode { 6876479Swpaul CXL_MODE_CXL, 6976479Swpaul CXL_MODE_PCI, 7076479Swpaul}; 7176479Swpaul 7276479Swpaul#define CXL_MODE_NO_DMA 0 7378323Swpaul#define CXL_MODE_DMA_TVT0 1 7478323Swpaul#define CXL_MODE_DMA_TVT1 2 7578323Swpaul 7678323Swpaulint cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode, 7778323Swpaul unsigned long flags); 7878323Swpaul 7978323Swpaul 8078323Swpaul/* 8178323Swpaul * Set the device for capi DMA. 8278323Swpaul * Define its dma_ops and dma offset so that allocations will be using TVT#1 8378323Swpaul * 8478323Swpaul * Input: 8578323Swpaul * dev: device to set 8678323Swpaul * flags: options. CXL_MODE_DMA_TVT1 should be used 8778323Swpaul */ 8878323Swpaulint cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags); 8976479Swpaul 9076479Swpaul 91150968Sglebius/* 92150968Sglebius * Get the Process Element structure for the given thread 93150968Sglebius * 94150968Sglebius * Input: 9576479Swpaul * task: task_struct for the context of the translation 9676479Swpaul * translation_mode: whether addresses should be translated 97192506Syongari * Output: 98192506Syongari * attr: attributes to fill up the Process Element structure from CAIA 99192506Syongari */ 100192506Syongaristruct cxllib_pe_attributes { 101192506Syongari u64 sr; 10276479Swpaul u32 lpid; 103129879Sphk u32 tid; 104192506Syongari u32 pid; 105192506Syongari}; 10676479Swpaul#define CXL_TRANSLATED_MODE 0 107192506Syongari#define CXL_REAL_MODE 1 108192506Syongari 10976479Swpaulint cxllib_get_PE_attributes(struct task_struct *task, 110192506Syongari unsigned long translation_mode, struct cxllib_pe_attributes *attr); 11176479Swpaul 11276479Swpaul 11376479Swpaul/* 11476479Swpaul * Handle memory fault. 11576479Swpaul * Fault in all the pages of the specified buffer for the permissions 11676479Swpaul * provided in ���flags��� 11776479Swpaul * 11876479Swpaul * Shouldn't be called from interrupt context 11976479Swpaul * 120227277Smarius * Input: 12176479Swpaul * mm: struct mm for the thread faulting the pages 12276479Swpaul * addr: base address of the buffer to page in 123119285Simp * size: size of the buffer to page in 124119285Simp * flags: permission requested (DSISR_ISSTORE...) 12576479Swpaul */ 126192506Syongariint cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags); 12776479Swpaul 12876522Swpaul 12976479Swpaul#endif /* _MISC_CXLLIB_H */ 130192506Syongari