Searched refs:reg_offset (Results 176 - 200 of 376) sorted by relevance

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/linux-master/drivers/crypto/hisilicon/zip/
H A Dzip_main.c338 .reg_offset = HZIP_CORE_DFX_BASE,
341 .reg_offset = HZIP_CORE_DFX_COMP_0,
344 .reg_offset = HZIP_CORE_DFX_COMP_1,
347 .reg_offset = HZIP_CORE_DFX_DECOMP_0,
350 .reg_offset = HZIP_CORE_DFX_DECOMP_1,
353 .reg_offset = HZIP_CORE_DFX_DECOMP_2,
356 .reg_offset = HZIP_CORE_DFX_DECOMP_3,
359 .reg_offset = HZIP_CORE_DFX_DECOMP_4,
362 .reg_offset = HZIP_CORE_DFX_DECOMP_5,
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v6_1.c59 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
61 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
281 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
H A Dnbio_v2_3.c70 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
72 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
344 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
H A Dvi.c747 u32 sh_num, u32 reg_offset)
754 switch (reg_offset) {
769 val = RREG32(reg_offset);
778 switch (reg_offset) {
815 idx = (reg_offset - mmGB_TILE_MODE0);
833 idx = (reg_offset - mmGB_MACROTILE_MODE0);
836 return RREG32(reg_offset);
842 u32 sh_num, u32 reg_offset, u32 *value)
850 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
745 vi_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) argument
841 vi_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) argument
[all...]
/linux-master/drivers/misc/mchp_pci1xxxx/
H A Dmchp_pci1xxxx_gpio.c63 static inline void pci1xxx_assign_bit(void __iomem *base_addr, unsigned int reg_offset, argument
68 data = readl(base_addr + reg_offset);
73 writel(data, base_addr + reg_offset);
/linux-master/drivers/net/wireless/ath/ath10k/
H A Dsnoc.c76 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
81 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
86 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
91 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
96 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
101 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
106 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
111 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
116 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
121 .reg_offset
[all...]
/linux-master/drivers/gpio/
H A Dgpio-uniphier.c100 unsigned int bank, reg_offset; local
104 reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
106 return !!(readl(priv->regs + reg_offset) & mask);
H A Dgpio-tangier.c67 u8 reg_offset = offset / 32; local
69 return priv->reg_base + reg + reg_offset * 4;
76 u8 reg_offset = offset / 32; local
80 return priv->reg_base + reg + reg_offset * 4;
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_packet_manager_v9.c295 uint32_t reg_offset = 0; local
302 &reg_offset,
318 packet->bitfields3.dst_mmreg_addr = reg_offset;
/linux-master/drivers/soc/ti/
H A Dpruss.c311 u32 reg_offset; local
344 ret = of_property_read_u32(clk_mux_np, "reg", &reg_offset);
348 reg = pruss->cfg_base + reg_offset;
/linux-master/drivers/net/ethernet/broadcom/asp2/
H A Dbcmasp_ethtool.c22 u32 reg_offset; member in struct:bcmasp_stats
33 .reg_offset = offset, \
88 return s->reg_offset;
/linux-master/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-core.c286 .reg_offset = 0,
300 .reg_offset = 0x2000,
314 .reg_offset = 0,
/linux-master/drivers/pinctrl/
H A Dpinctrl-ingenic.c116 unsigned int reg_offset; member in struct:ingenic_chip_info
254 .reg_offset = 0x30,
363 .reg_offset = 0x100,
465 .reg_offset = 0x100,
602 .reg_offset = 0x100,
767 .reg_offset = 0x100,
1115 .reg_offset = 0x100,
1455 .reg_offset = 0x100,
1728 .reg_offset = 0x100,
1992 .reg_offset
[all...]
/linux-master/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c262 u8 reg_offset; member in struct:lpc18xx_cgu_pll_clk
273 .reg_offset = LPC18XX_CGU_ ##_id ##_STAT, \
585 clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;
586 clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;
/linux-master/drivers/pinctrl/mediatek/
H A Dmtk-eint.c104 unsigned int reg_offset; local
114 reg_offset = eint->regs->pol_clr;
116 reg_offset = eint->regs->pol_set;
117 writel(mask, reg + reg_offset);
/linux-master/drivers/net/ethernet/broadcom/
H A Dbcmsysport.h622 .reg_offset = ofs, \
630 .reg_offset = ofs, \
638 .reg_offset = ofs, \
650 u16 reg_offset; member in struct:bcm_sysport_stats
/linux-master/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_misc.c637 u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0); local
668 ret = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset,
674 dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
678 dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
/linux-master/drivers/mfd/
H A Dmax77650.c99 .reg_offset = MAX77650_INT_GLBL_OFFSET,
/linux-master/drivers/clk/ti/
H A Dclkctrl.c51 u16 reg_offset; member in struct:omap_clkctrl_clk
237 if (iter->reg_offset == clkspec->args[0] &&
318 clkctrl_clk->reg_offset = offset;
697 clkctrl_clk->reg_offset = reg_data->offset;
/linux-master/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c187 this->reg_base = gfx->conf_reg_base + gfx->gfxpll.reg_offset;
/linux-master/drivers/base/regmap/
H A Dregmap-debugfs.c104 unsigned int reg_offset; local
167 reg_offset = fpos_offset / map->debugfs_tot_len;
168 *pos = c->min + (reg_offset * map->debugfs_tot_len);
170 return c->base_reg + (reg_offset * map->reg_stride);
/linux-master/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_ctl.c42 u32 reg_offset; member in struct:mdp5_ctl
87 (void)ctl->reg_offset; /* TODO use this instead of mdp5_write */
96 (void)ctl->reg_offset; /* TODO use this instead of mdp5_write */
727 ctl->reg_offset = ctl_cfg->base[c];
/linux-master/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.h108 * @reg_offset: offsets of configuration registers (don't care of width is 0)
112 u8 reg_offset[PINCFG_TYPE_NUM]; member in struct:samsung_pin_bank_type
/linux-master/drivers/net/ipa/
H A Dipa_uc.c247 iowrite32(val, ipa->reg_virt + reg_offset(reg));
/linux-master/arch/x86/math-emu/
H A Dget_address.c32 static int reg_offset[] = { variable
43 #define REG_(x) (*(long *)(reg_offset[(x)] + (u_char *)FPU_info->regs))

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