1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Broadcom BCM7xxx System Port Ethernet MAC driver 4 * 5 * Copyright (C) 2014 Broadcom Corporation 6 */ 7 8#ifndef __BCM_SYSPORT_H 9#define __BCM_SYSPORT_H 10 11#include <linux/bitmap.h> 12#include <linux/ethtool.h> 13#include <linux/if_vlan.h> 14#include <linux/dim.h> 15 16#include "unimac.h" 17 18/* Receive/transmit descriptor format */ 19#define DESC_ADDR_HI_STATUS_LEN 0x00 20#define DESC_ADDR_HI_SHIFT 0 21#define DESC_ADDR_HI_MASK 0xff 22#define DESC_STATUS_SHIFT 8 23#define DESC_STATUS_MASK 0x3ff 24#define DESC_LEN_SHIFT 18 25#define DESC_LEN_MASK 0x7fff 26#define DESC_ADDR_LO 0x04 27 28/* HW supports 40-bit addressing hence the */ 29#define DESC_SIZE (WORDS_PER_DESC * sizeof(u32)) 30 31/* Default RX buffer allocation size */ 32#define RX_BUF_LENGTH 2048 33 34/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526. 35 * 1536 is multiple of 256 bytes 36 */ 37#define ENET_BRCM_TAG_LEN 4 38#define ENET_PAD 10 39#define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 40 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 41 42/* Transmit status block */ 43struct bcm_tsb { 44 u32 pcp_dei_vid; 45#define PCP_DEI_MASK 0xf 46#define VID_SHIFT 4 47#define VID_MASK 0xfff 48 u32 l4_ptr_dest_map; 49#define L4_CSUM_PTR_MASK 0x1ff 50#define L4_PTR_SHIFT 9 51#define L4_PTR_MASK 0x1ff 52#define L4_UDP (1 << 18) 53#define L4_LENGTH_VALID (1 << 19) 54#define DEST_MAP_SHIFT 20 55#define DEST_MAP_MASK 0x1ff 56}; 57 58/* Receive status block uses the same 59 * definitions as the DMA descriptor 60 */ 61struct bcm_rsb { 62 u32 rx_status_len; 63 u32 brcm_egress_tag; 64}; 65 66/* Common Receive/Transmit status bits */ 67#define DESC_L4_CSUM (1 << 7) 68#define DESC_SOP (1 << 8) 69#define DESC_EOP (1 << 9) 70 71/* Receive Status bits */ 72#define RX_STATUS_UCAST 0 73#define RX_STATUS_BCAST 0x04 74#define RX_STATUS_MCAST 0x08 75#define RX_STATUS_L2_MCAST 0x0c 76#define RX_STATUS_ERR (1 << 4) 77#define RX_STATUS_OVFLOW (1 << 5) 78#define RX_STATUS_PARSE_FAIL (1 << 6) 79 80/* Transmit Status bits */ 81#define TX_STATUS_VLAN_NO_ACT 0x00 82#define TX_STATUS_VLAN_PCP_TSB 0x01 83#define TX_STATUS_VLAN_QUEUE 0x02 84#define TX_STATUS_VLAN_VID_TSB 0x03 85#define TX_STATUS_OWR_CRC (1 << 2) 86#define TX_STATUS_APP_CRC (1 << 3) 87#define TX_STATUS_BRCM_TAG_NO_ACT 0 88#define TX_STATUS_BRCM_TAG_ZERO 0x10 89#define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20 90#define TX_STATUS_BRCM_TAG_ONE_TSB 0x30 91#define TX_STATUS_SKIP_BYTES (1 << 6) 92 93/* Specific register definitions */ 94#define SYS_PORT_TOPCTRL_OFFSET 0 95#define REV_CNTL 0x00 96#define REV_MASK 0xffff 97 98#define RX_FLUSH_CNTL 0x04 99#define RX_FLUSH (1 << 0) 100 101#define TX_FLUSH_CNTL 0x08 102#define TX_FLUSH (1 << 0) 103 104#define MISC_CNTL 0x0c 105#define SYS_CLK_SEL (1 << 0) 106#define TDMA_EOP_SEL (1 << 1) 107 108/* Level-2 Interrupt controller offsets and defines */ 109#define SYS_PORT_INTRL2_0_OFFSET 0x200 110#define SYS_PORT_INTRL2_1_OFFSET 0x240 111#define INTRL2_CPU_STATUS 0x00 112#define INTRL2_CPU_SET 0x04 113#define INTRL2_CPU_CLEAR 0x08 114#define INTRL2_CPU_MASK_STATUS 0x0c 115#define INTRL2_CPU_MASK_SET 0x10 116#define INTRL2_CPU_MASK_CLEAR 0x14 117 118/* Level-2 instance 0 interrupt bits */ 119#define INTRL2_0_GISB_ERR (1 << 0) 120#define INTRL2_0_RBUF_OVFLOW (1 << 1) 121#define INTRL2_0_TBUF_UNDFLOW (1 << 2) 122#define INTRL2_0_MPD (1 << 3) 123#define INTRL2_0_BRCM_MATCH_TAG (1 << 4) 124#define INTRL2_0_RDMA_MBDONE (1 << 5) 125#define INTRL2_0_OVER_MAX_THRESH (1 << 6) 126#define INTRL2_0_BELOW_HYST_THRESH (1 << 7) 127#define INTRL2_0_FREE_LIST_EMPTY (1 << 8) 128#define INTRL2_0_TX_RING_FULL (1 << 9) 129#define INTRL2_0_DESC_ALLOC_ERR (1 << 10) 130#define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11) 131 132/* SYSTEMPORT Lite groups the TX queues interrupts on instance 0 */ 133#define INTRL2_0_TDMA_MBDONE_SHIFT 12 134#define INTRL2_0_TDMA_MBDONE_MASK (0xffff << INTRL2_0_TDMA_MBDONE_SHIFT) 135 136/* RXCHK offset and defines */ 137#define SYS_PORT_RXCHK_OFFSET 0x300 138 139#define RXCHK_CONTROL 0x00 140#define RXCHK_EN (1 << 0) 141#define RXCHK_SKIP_FCS (1 << 1) 142#define RXCHK_BAD_CSUM_DIS (1 << 2) 143#define RXCHK_BRCM_TAG_EN (1 << 3) 144#define RXCHK_BRCM_TAG_MATCH_SHIFT 4 145#define RXCHK_BRCM_TAG_MATCH_MASK 0xff 146#define RXCHK_PARSE_TNL (1 << 12) 147#define RXCHK_VIOL_EN (1 << 13) 148#define RXCHK_VIOL_DIS (1 << 14) 149#define RXCHK_INCOM_PKT (1 << 15) 150#define RXCHK_V6_DUPEXT_EN (1 << 16) 151#define RXCHK_V6_DUPEXT_DIS (1 << 17) 152#define RXCHK_ETHERTYPE_DIS (1 << 18) 153#define RXCHK_L2_HDR_DIS (1 << 19) 154#define RXCHK_L3_HDR_DIS (1 << 20) 155#define RXCHK_MAC_RX_ERR_DIS (1 << 21) 156#define RXCHK_PARSE_AUTH (1 << 22) 157 158#define RXCHK_BRCM_TAG0 0x04 159#define RXCHK_BRCM_TAG(i) ((i) * 0x4 + RXCHK_BRCM_TAG0) 160#define RXCHK_BRCM_TAG0_MASK 0x24 161#define RXCHK_BRCM_TAG_MASK(i) ((i) * 0x4 + RXCHK_BRCM_TAG0_MASK) 162#define RXCHK_BRCM_TAG_MATCH_STATUS 0x44 163#define RXCHK_ETHERTYPE 0x48 164#define RXCHK_BAD_CSUM_CNTR 0x4C 165#define RXCHK_OTHER_DISC_CNTR 0x50 166 167#define RXCHK_BRCM_TAG_MAX 8 168#define RXCHK_BRCM_TAG_CID_SHIFT 16 169#define RXCHK_BRCM_TAG_CID_MASK 0xff 170 171/* TXCHCK offsets and defines */ 172#define SYS_PORT_TXCHK_OFFSET 0x380 173#define TXCHK_PKT_RDY_THRESH 0x00 174 175/* Receive buffer offset and defines */ 176#define SYS_PORT_RBUF_OFFSET 0x400 177 178#define RBUF_CONTROL 0x00 179#define RBUF_RSB_EN (1 << 0) 180#define RBUF_4B_ALGN (1 << 1) 181#define RBUF_BRCM_TAG_STRIP (1 << 2) 182#define RBUF_BAD_PKT_DISC (1 << 3) 183#define RBUF_RESUME_THRESH_SHIFT 4 184#define RBUF_RESUME_THRESH_MASK 0xff 185#define RBUF_OK_TO_SEND_SHIFT 12 186#define RBUF_OK_TO_SEND_MASK 0xff 187#define RBUF_CRC_REPLACE (1 << 20) 188#define RBUF_OK_TO_SEND_MODE (1 << 21) 189/* SYSTEMPORT Lite uses two bits here */ 190#define RBUF_RSB_SWAP0 (1 << 22) 191#define RBUF_RSB_SWAP1 (1 << 23) 192#define RBUF_ACPI_EN (1 << 23) 193#define RBUF_ACPI_EN_LITE (1 << 24) 194 195#define RBUF_PKT_RDY_THRESH 0x04 196 197#define RBUF_STATUS 0x08 198#define RBUF_WOL_MODE (1 << 0) 199#define RBUF_MPD (1 << 1) 200#define RBUF_ACPI (1 << 2) 201 202#define RBUF_OVFL_DISC_CNTR 0x0c 203#define RBUF_ERR_PKT_CNTR 0x10 204 205/* Transmit buffer offset and defines */ 206#define SYS_PORT_TBUF_OFFSET 0x600 207 208#define TBUF_CONTROL 0x00 209#define TBUF_BP_EN (1 << 0) 210#define TBUF_MAX_PKT_THRESH_SHIFT 1 211#define TBUF_MAX_PKT_THRESH_MASK 0x1f 212#define TBUF_FULL_THRESH_SHIFT 8 213#define TBUF_FULL_THRESH_MASK 0x1f 214 215/* UniMAC offset and defines */ 216#define SYS_PORT_UMAC_OFFSET 0x800 217 218#define UMAC_MIB_START 0x400 219 220/* There is a 0xC gap between the end of RX and beginning of TX stats and then 221 * between the end of TX stats and the beginning of the RX RUNT 222 */ 223#define UMAC_MIB_STAT_OFFSET 0xc 224 225#define UMAC_MIB_CTRL 0x580 226#define MIB_RX_CNT_RST (1 << 0) 227#define MIB_RUNT_CNT_RST (1 << 1) 228#define MIB_TX_CNT_RST (1 << 2) 229 230/* These offsets are valid for SYSTEMPORT and SYSTEMPORT Lite */ 231#define UMAC_MPD_CTRL 0x620 232#define MPD_EN (1 << 0) 233#define MSEQ_LEN_SHIFT 16 234#define MSEQ_LEN_MASK 0xff 235#define PSW_EN (1 << 27) 236 237#define UMAC_PSW_MS 0x624 238#define UMAC_PSW_LS 0x628 239#define UMAC_MDF_CTRL 0x650 240#define UMAC_MDF_ADDR 0x654 241 242/* Only valid on SYSTEMPORT Lite */ 243#define SYS_PORT_GIB_OFFSET 0x1000 244 245#define GIB_CONTROL 0x00 246#define GIB_TX_EN (1 << 0) 247#define GIB_RX_EN (1 << 1) 248#define GIB_TX_FLUSH (1 << 2) 249#define GIB_RX_FLUSH (1 << 3) 250#define GIB_GTX_CLK_SEL_SHIFT 4 251#define GIB_GTX_CLK_EXT_CLK (0 << GIB_GTX_CLK_SEL_SHIFT) 252#define GIB_GTX_CLK_125MHZ (1 << GIB_GTX_CLK_SEL_SHIFT) 253#define GIB_GTX_CLK_250MHZ (2 << GIB_GTX_CLK_SEL_SHIFT) 254#define GIB_FCS_STRIP_SHIFT 6 255#define GIB_FCS_STRIP (1 << GIB_FCS_STRIP_SHIFT) 256#define GIB_LCL_LOOP_EN (1 << 7) 257#define GIB_LCL_LOOP_TXEN (1 << 8) 258#define GIB_RMT_LOOP_EN (1 << 9) 259#define GIB_RMT_LOOP_RXEN (1 << 10) 260#define GIB_RX_PAUSE_EN (1 << 11) 261#define GIB_PREAMBLE_LEN_SHIFT 12 262#define GIB_PREAMBLE_LEN_MASK 0xf 263#define GIB_IPG_LEN_SHIFT 16 264#define GIB_IPG_LEN_MASK 0x3f 265#define GIB_PAD_EXTENSION_SHIFT 22 266#define GIB_PAD_EXTENSION_MASK 0x3f 267 268#define GIB_MAC1 0x08 269#define GIB_MAC0 0x0c 270 271/* Receive DMA offset and defines */ 272#define SYS_PORT_RDMA_OFFSET 0x2000 273 274#define RDMA_CONTROL 0x1000 275#define RDMA_EN (1 << 0) 276#define RDMA_RING_CFG (1 << 1) 277#define RDMA_DISC_EN (1 << 2) 278#define RDMA_BUF_DATA_OFFSET_SHIFT 4 279#define RDMA_BUF_DATA_OFFSET_MASK 0x3ff 280 281#define RDMA_STATUS 0x1004 282#define RDMA_DISABLED (1 << 0) 283#define RDMA_DESC_RAM_INIT_BUSY (1 << 1) 284#define RDMA_BP_STATUS (1 << 2) 285 286#define RDMA_SCB_BURST_SIZE 0x1008 287 288#define RDMA_RING_BUF_SIZE 0x100c 289#define RDMA_RING_SIZE_SHIFT 16 290 291#define RDMA_WRITE_PTR_HI 0x1010 292#define RDMA_WRITE_PTR_LO 0x1014 293#define RDMA_OVFL_DISC_CNTR 0x1018 294#define RDMA_PROD_INDEX 0x1018 295#define RDMA_PROD_INDEX_MASK 0xffff 296 297#define RDMA_CONS_INDEX 0x101c 298#define RDMA_CONS_INDEX_MASK 0xffff 299 300#define RDMA_START_ADDR_HI 0x1020 301#define RDMA_START_ADDR_LO 0x1024 302#define RDMA_END_ADDR_HI 0x1028 303#define RDMA_END_ADDR_LO 0x102c 304 305#define RDMA_MBDONE_INTR 0x1030 306#define RDMA_INTR_THRESH_MASK 0x1ff 307#define RDMA_TIMEOUT_SHIFT 16 308#define RDMA_TIMEOUT_MASK 0xffff 309 310#define RDMA_XON_XOFF_THRESH 0x1034 311#define RDMA_XON_XOFF_THRESH_MASK 0xffff 312#define RDMA_XOFF_THRESH_SHIFT 16 313 314#define RDMA_READ_PTR_HI 0x1038 315#define RDMA_READ_PTR_LO 0x103c 316 317#define RDMA_OVERRIDE 0x1040 318#define RDMA_LE_MODE (1 << 0) 319#define RDMA_REG_MODE (1 << 1) 320 321#define RDMA_TEST 0x1044 322#define RDMA_TP_OUT_SEL (1 << 0) 323#define RDMA_MEM_SEL (1 << 1) 324 325#define RDMA_DEBUG 0x1048 326 327/* Transmit DMA offset and defines */ 328#define TDMA_NUM_RINGS 32 /* rings = queues */ 329#define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */ 330 331#define SYS_PORT_TDMA_OFFSET 0x4000 332#define TDMA_WRITE_PORT_OFFSET 0x0000 333#define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \ 334 (i) * TDMA_PORT_SIZE) 335#define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \ 336 sizeof(u32) + (i) * TDMA_PORT_SIZE) 337 338#define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \ 339 (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) 340#define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \ 341 (i) * TDMA_PORT_SIZE) 342#define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \ 343 sizeof(u32) + (i) * TDMA_PORT_SIZE) 344 345#define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \ 346 (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) 347#define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \ 348 (i) * sizeof(u32)) 349 350#define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \ 351 (TDMA_NUM_RINGS * sizeof(u32))) 352 353/* Register offsets and defines relatives to a specific ring number */ 354#define RING_HEAD_TAIL_PTR 0x00 355#define RING_HEAD_MASK 0x7ff 356#define RING_TAIL_SHIFT 11 357#define RING_TAIL_MASK 0x7ff 358#define RING_FLUSH (1 << 24) 359#define RING_EN (1 << 25) 360 361#define RING_COUNT 0x04 362#define RING_COUNT_MASK 0x7ff 363#define RING_BUFF_DONE_SHIFT 11 364#define RING_BUFF_DONE_MASK 0x7ff 365 366#define RING_MAX_HYST 0x08 367#define RING_MAX_THRESH_MASK 0x7ff 368#define RING_HYST_THRESH_SHIFT 11 369#define RING_HYST_THRESH_MASK 0x7ff 370 371#define RING_INTR_CONTROL 0x0c 372#define RING_INTR_THRESH_MASK 0x7ff 373#define RING_EMPTY_INTR_EN (1 << 15) 374#define RING_TIMEOUT_SHIFT 16 375#define RING_TIMEOUT_MASK 0xffff 376 377#define RING_PROD_CONS_INDEX 0x10 378#define RING_PROD_INDEX_MASK 0xffff 379#define RING_CONS_INDEX_SHIFT 16 380#define RING_CONS_INDEX_MASK 0xffff 381 382#define RING_MAPPING 0x14 383#define RING_QID_MASK 0x7 384#define RING_PORT_ID_SHIFT 3 385#define RING_PORT_ID_MASK 0x7 386#define RING_IGNORE_STATUS (1 << 6) 387#define RING_FAILOVER_EN (1 << 7) 388#define RING_CREDIT_SHIFT 8 389#define RING_CREDIT_MASK 0xffff 390 391#define RING_PCP_DEI_VID 0x18 392#define RING_VID_MASK 0x7ff 393#define RING_DEI (1 << 12) 394#define RING_PCP_SHIFT 13 395#define RING_PCP_MASK 0x7 396#define RING_PKT_SIZE_ADJ_SHIFT 16 397#define RING_PKT_SIZE_ADJ_MASK 0xf 398 399#define TDMA_DESC_RING_SIZE 28 400 401/* Defininition for a given TX ring base address */ 402#define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \ 403 ((i) * TDMA_DESC_RING_SIZE)) 404 405/* Ring indexed register addreses */ 406#define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \ 407 RING_HEAD_TAIL_PTR) 408#define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \ 409 RING_COUNT) 410#define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \ 411 RING_MAX_HYST) 412#define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \ 413 RING_INTR_CONTROL) 414#define TDMA_DESC_RING_PROD_CONS_INDEX(i) \ 415 (TDMA_DESC_RING_BASE(i) + \ 416 RING_PROD_CONS_INDEX) 417#define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \ 418 RING_MAPPING) 419#define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \ 420 RING_PCP_DEI_VID) 421 422#define TDMA_CONTROL 0x600 423#define TDMA_EN 0 424#define TSB_EN 1 425/* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we 426 * keep the SYSTEMPORT layout here and adjust with tdma_control_bit() 427 */ 428#define TSB_SWAP0 2 429#define TSB_SWAP1 3 430#define ACB_ALGO 3 431#define BUF_DATA_OFFSET_SHIFT 4 432#define BUF_DATA_OFFSET_MASK 0x3ff 433#define VLAN_EN 14 434#define SW_BRCM_TAG 15 435#define WNC_KPT_SIZE_UPDATE 16 436#define SYNC_PKT_SIZE 17 437#define ACH_TXDONE_DELAY_SHIFT 18 438#define ACH_TXDONE_DELAY_MASK 0xff 439 440#define TDMA_STATUS 0x604 441#define TDMA_DISABLED (1 << 0) 442#define TDMA_LL_RAM_INIT_BUSY (1 << 1) 443 444#define TDMA_SCB_BURST_SIZE 0x608 445#define TDMA_OVER_MAX_THRESH_STATUS 0x60c 446#define TDMA_OVER_HYST_THRESH_STATUS 0x610 447#define TDMA_TPID 0x614 448 449#define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618 450#define TDMA_FREE_HEAD_MASK 0x7ff 451#define TDMA_FREE_TAIL_SHIFT 11 452#define TDMA_FREE_TAIL_MASK 0x7ff 453 454#define TDMA_FREE_LIST_COUNT 0x61c 455#define TDMA_FREE_LIST_COUNT_MASK 0x7ff 456 457#define TDMA_TIER2_ARB_CTRL 0x620 458#define TDMA_ARB_MODE_RR 0 459#define TDMA_ARB_MODE_WEIGHT_RR 0x1 460#define TDMA_ARB_MODE_STRICT 0x2 461#define TDMA_ARB_MODE_DEFICIT_RR 0x3 462#define TDMA_CREDIT_SHIFT 4 463#define TDMA_CREDIT_MASK 0xffff 464 465#define TDMA_TIER1_ARB_0_CTRL 0x624 466#define TDMA_ARB_EN (1 << 0) 467 468#define TDMA_TIER1_ARB_0_QUEUE_EN 0x628 469#define TDMA_TIER1_ARB_1_CTRL 0x62c 470#define TDMA_TIER1_ARB_1_QUEUE_EN 0x630 471#define TDMA_TIER1_ARB_2_CTRL 0x634 472#define TDMA_TIER1_ARB_2_QUEUE_EN 0x638 473#define TDMA_TIER1_ARB_3_CTRL 0x63c 474#define TDMA_TIER1_ARB_3_QUEUE_EN 0x640 475 476#define TDMA_SCB_ENDIAN_OVERRIDE 0x644 477#define TDMA_LE_MODE (1 << 0) 478#define TDMA_REG_MODE (1 << 1) 479 480#define TDMA_TEST 0x648 481#define TDMA_TP_OUT_SEL (1 << 0) 482#define TDMA_MEM_TM (1 << 1) 483 484#define TDMA_DEBUG 0x64c 485 486/* Number of Receive hardware descriptor words */ 487#define SP_NUM_HW_RX_DESC_WORDS 1024 488#define SP_LT_NUM_HW_RX_DESC_WORDS 512 489 490/* Internal linked-list RAM size */ 491#define SP_NUM_TX_DESC 1536 492#define SP_LT_NUM_TX_DESC 256 493 494#define WORDS_PER_DESC 2 495 496/* Rx/Tx common counter group.*/ 497struct bcm_sysport_pkt_counters { 498 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 499 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 500 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 501 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 502 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 503 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 504 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 505 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 506 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 507 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 508}; 509 510/* RSV, Receive Status Vector */ 511struct bcm_sysport_rx_counters { 512 struct bcm_sysport_pkt_counters pkt_cnt; 513 u32 pkt; /* RO (0x428) Received pkt count*/ 514 u32 bytes; /* RO Received byte count */ 515 u32 mca; /* RO # of Received multicast pkt */ 516 u32 bca; /* RO # of Receive broadcast pkt */ 517 u32 fcs; /* RO # of Received FCS error */ 518 u32 cf; /* RO # of Received control frame pkt*/ 519 u32 pf; /* RO # of Received pause frame pkt */ 520 u32 uo; /* RO # of unknown op code pkt */ 521 u32 aln; /* RO # of alignment error count */ 522 u32 flr; /* RO # of frame length out of range count */ 523 u32 cde; /* RO # of code error pkt */ 524 u32 fcr; /* RO # of carrier sense error pkt */ 525 u32 ovr; /* RO # of oversize pkt*/ 526 u32 jbr; /* RO # of jabber count */ 527 u32 mtue; /* RO # of MTU error pkt*/ 528 u32 pok; /* RO # of Received good pkt */ 529 u32 uc; /* RO # of unicast pkt */ 530 u32 ppp; /* RO # of PPP pkt */ 531 u32 rcrc; /* RO (0x470),# of CRC match pkt */ 532}; 533 534/* TSV, Transmit Status Vector */ 535struct bcm_sysport_tx_counters { 536 struct bcm_sysport_pkt_counters pkt_cnt; 537 u32 pkts; /* RO (0x4a8) Transmited pkt */ 538 u32 mca; /* RO # of xmited multicast pkt */ 539 u32 bca; /* RO # of xmited broadcast pkt */ 540 u32 pf; /* RO # of xmited pause frame count */ 541 u32 cf; /* RO # of xmited control frame count */ 542 u32 fcs; /* RO # of xmited FCS error count */ 543 u32 ovr; /* RO # of xmited oversize pkt */ 544 u32 drf; /* RO # of xmited deferral pkt */ 545 u32 edf; /* RO # of xmited Excessive deferral pkt*/ 546 u32 scl; /* RO # of xmited single collision pkt */ 547 u32 mcl; /* RO # of xmited multiple collision pkt*/ 548 u32 lcl; /* RO # of xmited late collision pkt */ 549 u32 ecl; /* RO # of xmited excessive collision pkt*/ 550 u32 frg; /* RO # of xmited fragments pkt*/ 551 u32 ncl; /* RO # of xmited total collision count */ 552 u32 jbr; /* RO # of xmited jabber count*/ 553 u32 bytes; /* RO # of xmited byte count */ 554 u32 pok; /* RO # of xmited good pkt */ 555 u32 uc; /* RO (0x4f0) # of xmited unicast pkt */ 556}; 557 558struct bcm_sysport_mib { 559 struct bcm_sysport_rx_counters rx; 560 struct bcm_sysport_tx_counters tx; 561 u32 rx_runt_cnt; 562 u32 rx_runt_fcs; 563 u32 rx_runt_fcs_align; 564 u32 rx_runt_bytes; 565 u32 rxchk_bad_csum; 566 u32 rxchk_other_pkt_disc; 567 u32 rbuf_ovflow_cnt; 568 u32 rbuf_err_cnt; 569 u32 rdma_ovflow_cnt; 570 u32 alloc_rx_buff_failed; 571 u32 rx_dma_failed; 572 u32 tx_dma_failed; 573 u32 tx_realloc_tsb; 574 u32 tx_realloc_tsb_failed; 575}; 576 577/* HW maintains a large list of counters */ 578enum bcm_sysport_stat_type { 579 BCM_SYSPORT_STAT_NETDEV = -1, 580 BCM_SYSPORT_STAT_NETDEV64, 581 BCM_SYSPORT_STAT_MIB_RX, 582 BCM_SYSPORT_STAT_MIB_TX, 583 BCM_SYSPORT_STAT_RUNT, 584 BCM_SYSPORT_STAT_RXCHK, 585 BCM_SYSPORT_STAT_RBUF, 586 BCM_SYSPORT_STAT_RDMA, 587 BCM_SYSPORT_STAT_SOFT, 588}; 589 590/* Macros to help define ethtool statistics */ 591#define STAT_NETDEV(m) { \ 592 .stat_string = __stringify(m), \ 593 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 594 .stat_offset = offsetof(struct net_device_stats, m), \ 595 .type = BCM_SYSPORT_STAT_NETDEV, \ 596} 597 598#define STAT_NETDEV64(m) { \ 599 .stat_string = __stringify(m), \ 600 .stat_sizeof = sizeof(((struct bcm_sysport_stats64 *)0)->m), \ 601 .stat_offset = offsetof(struct bcm_sysport_stats64, m), \ 602 .type = BCM_SYSPORT_STAT_NETDEV64, \ 603} 604 605#define STAT_MIB(str, m, _type) { \ 606 .stat_string = str, \ 607 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 608 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 609 .type = _type, \ 610} 611 612#define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX) 613#define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX) 614#define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT) 615#define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT) 616 617#define STAT_RXCHK(str, m, ofs) { \ 618 .stat_string = str, \ 619 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 620 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 621 .type = BCM_SYSPORT_STAT_RXCHK, \ 622 .reg_offset = ofs, \ 623} 624 625#define STAT_RBUF(str, m, ofs) { \ 626 .stat_string = str, \ 627 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 628 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 629 .type = BCM_SYSPORT_STAT_RBUF, \ 630 .reg_offset = ofs, \ 631} 632 633#define STAT_RDMA(str, m, ofs) { \ 634 .stat_string = str, \ 635 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 636 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 637 .type = BCM_SYSPORT_STAT_RDMA, \ 638 .reg_offset = ofs, \ 639} 640 641/* TX bytes and packets */ 642#define NUM_SYSPORT_TXQ_STAT 2 643 644struct bcm_sysport_stats { 645 char stat_string[ETH_GSTRING_LEN]; 646 int stat_sizeof; 647 int stat_offset; 648 enum bcm_sysport_stat_type type; 649 /* reg offset from UMAC base for misc counters */ 650 u16 reg_offset; 651}; 652 653struct bcm_sysport_stats64 { 654 /* 64bit stats on 32bit/64bit Machine */ 655 u64 rx_packets; 656 u64 rx_bytes; 657 u64 tx_packets; 658 u64 tx_bytes; 659}; 660 661/* Software house keeping helper structure */ 662struct bcm_sysport_cb { 663 struct sk_buff *skb; /* SKB for RX packets */ 664 void __iomem *bd_addr; /* Buffer descriptor PHYS addr */ 665 666 DEFINE_DMA_UNMAP_ADDR(dma_addr); 667 DEFINE_DMA_UNMAP_LEN(dma_len); 668}; 669 670enum bcm_sysport_type { 671 SYSTEMPORT = 0, 672 SYSTEMPORT_LITE, 673}; 674 675struct bcm_sysport_hw_params { 676 bool is_lite; 677 unsigned int num_rx_desc_words; 678}; 679 680struct bcm_sysport_net_dim { 681 u16 use_dim; 682 u16 event_ctr; 683 unsigned long packets; 684 unsigned long bytes; 685 struct dim dim; 686}; 687 688/* Software view of the TX ring */ 689struct bcm_sysport_tx_ring { 690 spinlock_t lock; /* Ring lock for tx reclaim/xmit */ 691 struct napi_struct napi; /* NAPI per tx queue */ 692 unsigned int index; /* Ring index */ 693 unsigned int size; /* Ring current size */ 694 unsigned int alloc_size; /* Ring one-time allocated size */ 695 unsigned int desc_count; /* Number of descriptors */ 696 unsigned int curr_desc; /* Current descriptor */ 697 unsigned int c_index; /* Last consumer index */ 698 unsigned int clean_index; /* Current clean index */ 699 struct bcm_sysport_cb *cbs; /* Transmit control blocks */ 700 struct bcm_sysport_priv *priv; /* private context backpointer */ 701 unsigned long packets; /* packets statistics */ 702 unsigned long bytes; /* bytes statistics */ 703 unsigned int switch_queue; /* switch port queue number */ 704 unsigned int switch_port; /* switch port queue number */ 705 bool inspect; /* inspect switch port and queue */ 706}; 707 708/* Driver private structure */ 709struct bcm_sysport_priv { 710 void __iomem *base; 711 u32 irq0_stat; 712 u32 irq0_mask; 713 u32 irq1_stat; 714 u32 irq1_mask; 715 bool is_lite; 716 unsigned int num_rx_desc_words; 717 struct napi_struct napi ____cacheline_aligned; 718 struct net_device *netdev; 719 struct platform_device *pdev; 720 int irq0; 721 int irq1; 722 int wol_irq; 723 724 /* Transmit rings */ 725 spinlock_t desc_lock; 726 struct bcm_sysport_tx_ring *tx_rings; 727 728 /* Receive queue */ 729 void __iomem *rx_bds; 730 struct bcm_sysport_cb *rx_cbs; 731 unsigned int num_rx_bds; 732 unsigned int rx_read_ptr; 733 unsigned int rx_c_index; 734 735 struct bcm_sysport_net_dim dim; 736 u32 rx_max_coalesced_frames; 737 u32 rx_coalesce_usecs; 738 739 /* PHY device */ 740 struct device_node *phy_dn; 741 phy_interface_t phy_interface; 742 int old_pause; 743 int old_link; 744 int old_duplex; 745 746 /* Misc fields */ 747 unsigned int rx_chk_en:1; 748 unsigned int tsb_en:1; 749 unsigned int crc_fwd:1; 750 u16 rev; 751 u32 wolopts; 752 u8 sopass[SOPASS_MAX]; 753 unsigned int wol_irq_disabled:1; 754 struct clk *clk; 755 struct clk *wol_clk; 756 757 /* MIB related fields */ 758 struct bcm_sysport_mib mib; 759 760 /* Ethtool */ 761 u32 msg_enable; 762 DECLARE_BITMAP(filters, RXCHK_BRCM_TAG_MAX); 763 u32 filters_loc[RXCHK_BRCM_TAG_MAX]; 764 765 struct bcm_sysport_stats64 stats64; 766 767 /* For atomic update generic 64bit value on 32bit Machine */ 768 struct u64_stats_sync syncp; 769 770 /* map information between switch port queues and local queues */ 771 struct notifier_block netdev_notifier; 772 unsigned int per_port_num_tx_queues; 773 struct bcm_sysport_tx_ring *ring_map[DSA_MAX_PORTS * 8]; 774 775}; 776#endif /* __BCM_SYSPORT_H */ 777