/linux-master/drivers/clk/imx/ |
H A D | clk-scu.c | 10 #include <linux/clk-provider.h> 20 #include "clk-scu.h" 82 * @clk: clk type of this resource 90 u8 clk; member in struct:imx_sc_msg_req_set_clock_rate 95 u8 clk; member in struct:req_get_clock_rate 131 u8 clk; member in struct:imx_sc_msg_get_clock_parent::__anon158::req_get_clock_parent 149 u8 clk; member in struct:imx_sc_msg_set_clock_parent 157 * @clk: clk typ 166 u8 clk; member in struct:imx_sc_msg_req_clock_enable 232 struct clk_scu *clk = to_clk_scu(hw); local 293 struct clk_scu *clk = to_clk_scu(hw); local 323 struct clk_scu *clk = to_clk_scu(hw); local 341 struct clk_scu *clk = to_clk_scu(hw); local 368 struct clk_scu *clk = to_clk_scu(hw); local 394 sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource, u8 clk, bool enable, bool autog) argument 421 struct clk_scu *clk = to_clk_scu(hw); local 435 struct clk_scu *clk = to_clk_scu(hw); local 474 struct clk_scu *clk; local 526 struct imx_scu_clk_node *clk; local 539 struct imx_scu_clk_node *clk = dev_get_platdata(dev); local 582 struct clk_scu *clk = dev_get_drvdata(dev); local 616 struct clk_scu *clk = dev_get_drvdata(dev); local 691 struct imx_scu_clk_node clk = { local 742 struct imx_scu_clk_node *clk, *n; local 756 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); local 783 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); local 802 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); local 813 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); local 827 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); local 835 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); local 847 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw); local 870 struct clk_gpr_scu *clk; local [all...] |
/linux-master/sound/soc/mediatek/mt8183/ |
H A D | mt8183-afe-clk.c | 3 // mt8183-afe-clk.c -- Mediatek 8183 afe clock ctrl 8 #include <linux/clk.h> 11 #include "mt8183-afe-clk.h" 97 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), 99 if (!afe_priv->clk) 103 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); 104 if (IS_ERR(afe_priv->clk[i])) { 107 PTR_ERR(afe_priv->clk[i])); 108 return PTR_ERR(afe_priv->clk[ [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
H A D | gt215.c | 43 read_vco(struct gt215_clk *clk, int idx) argument 45 struct nvkm_device *device = clk->base.subdev.device; 52 return read_pll(clk, 0x41, 0x00e820); 54 return read_pll(clk, 0x42, 0x00e8a0); 61 read_clk(struct gt215_clk *clk, int idx, bool ignore_en) argument 63 struct nvkm_device *device = clk->base.subdev.device; 99 sclk = read_vco(clk, idx); 108 read_pll(struct gt215_clk *clk, int idx, u32 pll) argument 110 struct nvkm_device *device = clk->base.subdev.device; 128 sclk = read_clk(clk, 145 struct gt215_clk *clk = gt215_clk(base); local 190 struct gt215_clk *clk = gt215_clk(base); local 238 struct gt215_clk *clk = gt215_clk(base); local 274 calc_clk(struct gt215_clk *clk, struct nvkm_cstate *cstate, int idx, u32 pll, int dom) argument 285 calc_host(struct gt215_clk *clk, struct nvkm_cstate *cstate) argument 307 gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) argument 342 gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags) argument 355 disable_clk_src(struct gt215_clk *clk, u32 src) argument 363 prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom) argument 407 prog_clk(struct gt215_clk *clk, int idx, int dom) argument 415 prog_host(struct gt215_clk *clk) argument 443 prog_core(struct gt215_clk *clk, int dom) argument 461 struct gt215_clk *clk = gt215_clk(base); local 488 struct gt215_clk *clk = gt215_clk(base); local 543 struct gt215_clk *clk; local [all...] |
H A D | gk104.c | 50 read_vco(struct gk104_clk *clk, u32 dsrc) argument 52 struct nvkm_device *device = clk->base.subdev.device; 55 return read_pll(clk, 0x00e800); 56 return read_pll(clk, 0x00e820); 60 read_pll(struct gk104_clk *clk, u32 pll) argument 62 struct nvkm_device *device = clk->base.subdev.device; 81 sclk = read_pll(clk, 0x132020); 85 sclk = read_div(clk, 0, 0x137320, 0x137330); 92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); 106 read_div(struct gk104_clk *clk, in argument 133 read_mem(struct gk104_clk *clk) argument 145 read_clk(struct gk104_clk *clk, int idx) argument 191 struct gk104_clk *clk = gk104_clk(base); local 223 calc_div(struct gk104_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv) argument 234 calc_src(struct gk104_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv) argument 263 calc_pll(struct gk104_clk *clk, int idx, u32 freq, u32 *coef) argument 287 calc_clk(struct gk104_clk *clk, struct nvkm_cstate *cstate, int idx, int dom) argument 341 struct gk104_clk *clk = gk104_clk(base); local 357 gk104_clk_prog_0(struct gk104_clk *clk, int idx) argument 368 gk104_clk_prog_1_0(struct gk104_clk *clk, int idx) argument 379 gk104_clk_prog_1_1(struct gk104_clk *clk, int idx) argument 386 gk104_clk_prog_2(struct gk104_clk *clk, int idx) argument 411 gk104_clk_prog_3(struct gk104_clk *clk, int idx) argument 422 gk104_clk_prog_4_0(struct gk104_clk *clk, int idx) argument 437 gk104_clk_prog_4_1(struct gk104_clk *clk, int idx) argument 450 struct gk104_clk *clk = gk104_clk(base); local 481 struct gk104_clk *clk = gk104_clk(base); local 510 struct gk104_clk *clk; local [all...] |
H A D | gf100.c | 49 read_vco(struct gf100_clk *clk, u32 dsrc) argument 51 struct nvkm_device *device = clk->base.subdev.device; 54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); 55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); 59 read_pll(struct gf100_clk *clk, u32 pll) argument 61 struct nvkm_device *device = clk->base.subdev.device; 79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); 82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); 88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); 98 read_div(struct gf100_clk *clk, in argument 133 read_clk(struct gf100_clk *clk, int idx) argument 160 struct gf100_clk *clk = gf100_clk(base); local 210 calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv) argument 221 calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv) argument 250 calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef) argument 274 calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom) argument 327 struct gf100_clk *clk = gf100_clk(base); local 344 gf100_clk_prog_0(struct gf100_clk *clk, int idx) argument 355 gf100_clk_prog_1(struct gf100_clk *clk, int idx) argument 366 gf100_clk_prog_2(struct gf100_clk *clk, int idx) argument 393 gf100_clk_prog_3(struct gf100_clk *clk, int idx) argument 408 gf100_clk_prog_4(struct gf100_clk *clk, int idx) argument 418 struct gf100_clk *clk = gf100_clk(base); local 444 struct gf100_clk *clk = gf100_clk(base); local 474 struct gf100_clk *clk; local [all...] |
/linux-master/arch/arm/plat-orion/include/plat/ |
H A D | common.h | 20 struct clk *clk); 25 struct clk *clk); 30 struct clk *clk); 35 struct clk *clk); 101 struct clk *clk); [all...] |
/linux-master/arch/arm/mach-omap2/ |
H A D | omap_hwmod_2xxx_interconnect_data.c | 61 .clk = "uart1_ick", 69 .clk = "uart2_ick", 77 .clk = "uart3_ick", 85 .clk = "mcspi1_ick", 93 .clk = "mcspi2_ick", 101 .clk = "gpt3_ick", 109 .clk = "gpt4_ick", 117 .clk = "gpt5_ick", 125 .clk = "gpt6_ick", 133 .clk [all...] |
/linux-master/arch/mips/lantiq/xway/ |
H A D | gptu.c | 16 #include "../clk.h" 95 static int gptu_enable(struct clk *clk) argument 97 int ret = request_irq(irqres[clk->bits].start, timer_irq_handler, 105 GPTU_CON(clk->bits)); 106 gptu_w32(1, GPTU_RLD(clk->bits)); 107 gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN); 108 gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); 112 static void gptu_disable(struct clk *clk) argument 124 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); local 139 struct clk *clk; local [all...] |
/linux-master/drivers/clk/hisilicon/ |
H A D | clk-hix5hd2.c | 11 #include "clk.h" 171 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); local 174 val = readl_relaxed(clk->ctrl_reg); 175 val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; 176 writel_relaxed(val, clk->ctrl_reg); 177 val &= ~(clk->ctrl_rst_mask); 178 writel_relaxed(val, clk->ctrl_reg); 180 val = readl_relaxed(clk->phy_reg); 181 val |= clk 200 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); local 215 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); local 233 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); local 261 struct clk *clk; local [all...] |
/linux-master/drivers/clk/renesas/ |
H A D | clk-emev2.c | 8 #include <linux/clk-provider.h> 67 struct clk *clk; local 73 clk = clk_register_divider(NULL, np->name, parent_name, 0, 75 of_clk_add_provider(np, of_clk_src_simple_get, clk); 76 pr_debug("## %s %pOFn %p\n", __func__, np, clk); 84 struct clk *clk; local 90 clk = clk_register_gate(NULL, np->name, parent_name, 0, 92 of_clk_add_provider(np, of_clk_src_simple_get, clk); [all...] |
/linux-master/drivers/clk/qcom/ |
H A D | clk-branch.h | 8 #include <linux/clk-provider.h> 10 #include "clk-regmap.h" 70 struct clk_branch clk, bool on) 72 regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_CORE_ON, 77 struct clk_branch clk, bool on) 79 regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_ON, 84 struct clk_branch clk, bool on) 86 regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_OFF, 90 static inline void qcom_branch_set_wakeup(struct regmap *regmap, struct clk_branch clk, u32 val) argument 92 regmap_update_bits(regmap, clk 69 qcom_branch_set_force_mem_core(struct regmap *regmap, struct clk_branch clk, bool on) argument 76 qcom_branch_set_force_periph_on(struct regmap *regmap, struct clk_branch clk, bool on) argument 83 qcom_branch_set_force_periph_off(struct regmap *regmap, struct clk_branch clk, bool on) argument 96 qcom_branch_set_sleep(struct regmap *regmap, struct clk_branch clk, u32 val) argument [all...] |
/linux-master/drivers/clk/ |
H A D | clk-sp7021.c | 7 #include <linux/clk-provider.h> 146 static long plltv_integer_div(struct sp_pll *clk, unsigned long freq) argument 178 clk->p[SEL_FRA] = 0; 179 clk->p[DIVR] = r; 180 clk->p[DIVN] = n; 181 clk->p[DIVM] = m_table[m]; 187 __func__, clk_hw_get_name(&clk->hw), freq); 214 static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq) argument 278 clk->p[SEL_FRA] = 1; 279 clk 302 plltv_div(struct sp_pll *clk, unsigned long freq) argument 310 plltv_set_rate(struct sp_pll *clk) argument 374 plla_set_rate(struct sp_pll *clk) argument 388 plla_round_rate(struct sp_pll *clk, unsigned long rate) argument 403 sp_pll_calc_div(struct sp_pll *clk, unsigned long rate) argument 418 struct sp_pll *clk = to_sp_pll(hw); local 439 struct sp_pll *clk = to_sp_pll(hw); local 484 struct sp_pll *clk = to_sp_pll(hw); local 513 struct sp_pll *clk = to_sp_pll(hw); local 522 struct sp_pll *clk = to_sp_pll(hw); local 529 struct sp_pll *clk = to_sp_pll(hw); local [all...] |
H A D | clk-scmi.c | 8 #include <linux/clk-provider.h> 30 #define to_scmi_clk(clk) container_of(clk, struct scmi_clk, hw) 37 struct scmi_clk *clk = to_scmi_clk(hw); local 39 ret = scmi_proto_clk_ops->rate_get(clk->ph, clk->id, &rate); 49 struct scmi_clk *clk = to_scmi_clk(hw); local 57 if (clk->info->rate_discrete) 60 fmin = clk->info->range.min_rate; 61 fmax = clk 77 struct scmi_clk *clk = to_scmi_clk(hw); local 84 struct scmi_clk *clk = to_scmi_clk(hw); local 91 struct scmi_clk *clk = to_scmi_clk(hw); local 121 struct scmi_clk *clk = to_scmi_clk(hw); local 128 struct scmi_clk *clk = to_scmi_clk(hw); local 135 struct scmi_clk *clk = to_scmi_clk(hw); local 142 struct scmi_clk *clk = to_scmi_clk(hw); local 151 struct scmi_clk *clk = to_scmi_clk(hw); local [all...] |
H A D | clk-scpi.c | 8 #include <linux/clk-provider.h> 23 #define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw) 30 struct scpi_clk *clk = to_scpi_clk(hw); local 32 return clk->scpi_ops->clk_get_val(clk->id); 50 struct scpi_clk *clk = to_scpi_clk(hw); local 52 return clk->scpi_ops->clk_set_val(clk->id, rate); 62 static long __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigne argument 84 struct scpi_clk *clk = to_scpi_clk(hw); local 98 struct scpi_clk *clk = to_scpi_clk(hw); local 103 __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate) argument 117 struct scpi_clk *clk = to_scpi_clk(hw); local 170 struct scpi_clk **clk; member in struct:scpi_clk_data [all...] |
/linux-master/drivers/clk/meson/ |
H A D | sclk-div.c | 19 #include <linux/clk-provider.h> 22 #include "clk-regmap.h" 26 meson_sclk_div_data(struct clk_regmap *clk) argument 28 return (struct meson_sclk_div_data *)clk->data; 102 struct clk_regmap *clk = to_clk_regmap(hw); local 103 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); 112 static void sclk_apply_ratio(struct clk_regmap *clk, argument 122 meson_parm_write(clk->map, &sclk->hi, hi); 128 struct clk_regmap *clk = to_clk_regmap(hw); local 129 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); 142 struct clk_regmap *clk = to_clk_regmap(hw); local 158 sclk_apply_divider(struct clk_regmap *clk, struct meson_sclk_div_data *sclk) argument 170 struct clk_regmap *clk = to_clk_regmap(hw); local 185 struct clk_regmap *clk = to_clk_regmap(hw); local 193 struct clk_regmap *clk = to_clk_regmap(hw); local 203 struct clk_regmap *clk = to_clk_regmap(hw); local 211 struct clk_regmap *clk = to_clk_regmap(hw); local 222 struct clk_regmap *clk = to_clk_regmap(hw); local [all...] |
/linux-master/drivers/clk/st/ |
H A D | Makefile | 2 obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
|
H A D | clkgen-mux.c | 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 55 struct clk *clk; local 83 clk = clk_register_mux(NULL, np->name, parents, num_parents, 88 if (IS_ERR(clk)) 92 __clk_get_name(clk), 93 __clk_get_name(clk_get_parent(clk)), 94 (unsigned int)clk_get_rate(clk)); 97 of_clk_add_provider(np, of_clk_src_simple_get, clk); [all...] |
/linux-master/sound/soc/mediatek/mt2701/ |
H A D | mt2701-afe-common.h | 13 #include <linux/clk.h> 77 struct clk *hop_ck[MTK_STREAM_NUM]; 78 struct clk *sel_ck; 79 struct clk *div_ck; 80 struct clk *mclk_ck; 81 struct clk *asrco_ck; 91 struct clk *base_ck[MT2701_BASE_CLK_NUM]; 92 struct clk *mrgif_ck;
|
/linux-master/include/linux/mfd/wcd934x/ |
H A D | wcd934x.h | 5 #include <linux/clk.h> 26 struct clk *extclk;
|
/linux-master/drivers/clk/xilinx/ |
H A D | Makefile | 3 obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
|
/linux-master/drivers/gpu/drm/sti/ |
H A D | sti_compositor.h | 12 #include <linux/clk.h> 70 struct clk *clk_compo_main; 71 struct clk *clk_compo_aux; 72 struct clk *clk_pix_main; 73 struct clk *clk_pix_aux;
|
/linux-master/drivers/gpu/drm/mxsfb/ |
H A D | mxsfb_drv.h | 16 struct clk; 33 struct clk *clk; member in struct:mxsfb_drm_private 34 struct clk *clk_axi; 35 struct clk *clk_disp_axi;
|
/linux-master/sound/soc/mediatek/mt8186/ |
H A D | mt8186-afe-clk.c | 3 // mt8186-afe-clk.c -- Mediatek 8186 afe clock ctrl 8 #include <linux/clk.h> 13 #include "mt8186-afe-clk.h" 14 #include "mt8186-audsys-clk.h" 79 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], 80 afe_priv->clk[clk_id]); 97 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); 103 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], 104 afe_priv->clk[CLK_TOP_APLL1_CK]); 113 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG [all...] |
/linux-master/drivers/cpufreq/ |
H A D | armada-8k-cpufreq.c | 13 #include <linux/clk.h> 45 static void __init armada_8k_get_sharing_cpus(struct clk *cur_clk, 52 struct clk *clk; local 60 clk = clk_get(cpu_dev, NULL); 61 if (IS_ERR(clk)) { 64 if (clk_is_match(clk, cur_clk)) 67 clk_put(clk); 72 static int __init armada_8k_add_opp(struct clk *clk, struc argument 159 struct clk *clk; local [all...] |
/linux-master/drivers/clk/tegra/ |
H A D | clk-tegra-super-gen4.c | 7 #include <linux/clk-provider.h> 12 #include <linux/clk/tegra.h> 14 #include "clk.h" 15 #include "clk-id.h" 99 struct clk *clk; local 100 struct clk **dt_clk; 105 clk = tegra_clk_register_super_mux("sclk_mux", 111 *dt_clk = clk; 117 clk 171 struct clk *clk; local [all...] |