1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * mt2701-afe-common.h  --  Mediatek 2701 audio driver definitions
4 *
5 * Copyright (c) 2016 MediaTek Inc.
6 * Author: Garlic Tseng <garlic.tseng@mediatek.com>
7 */
8
9#ifndef _MT_2701_AFE_COMMON_H_
10#define _MT_2701_AFE_COMMON_H_
11
12#include <sound/soc.h>
13#include <linux/clk.h>
14#include <linux/regmap.h>
15#include "mt2701-reg.h"
16#include "../common/mtk-base-afe.h"
17
18#define MT2701_PLL_DOMAIN_0_RATE	98304000
19#define MT2701_PLL_DOMAIN_1_RATE	90316800
20
21enum {
22	MT2701_MEMIF_DL1,
23	MT2701_MEMIF_DL2,
24	MT2701_MEMIF_DL3,
25	MT2701_MEMIF_DL4,
26	MT2701_MEMIF_DL5,
27	MT2701_MEMIF_DL_SINGLE_NUM,
28	MT2701_MEMIF_DLM = MT2701_MEMIF_DL_SINGLE_NUM,
29	MT2701_MEMIF_UL1,
30	MT2701_MEMIF_UL2,
31	MT2701_MEMIF_UL3,
32	MT2701_MEMIF_UL4,
33	MT2701_MEMIF_UL5,
34	MT2701_MEMIF_DLBT,
35	MT2701_MEMIF_ULBT,
36	MT2701_MEMIF_NUM,
37	MT2701_IO_I2S = MT2701_MEMIF_NUM,
38	MT2701_IO_2ND_I2S,
39	MT2701_IO_3RD_I2S,
40	MT2701_IO_4TH_I2S,
41	MT2701_IO_5TH_I2S,
42	MT2701_IO_6TH_I2S,
43	MT2701_IO_MRG,
44};
45
46enum {
47	MT2701_IRQ_ASYS_IRQ1,
48	MT2701_IRQ_ASYS_IRQ2,
49	MT2701_IRQ_ASYS_IRQ3,
50	MT2701_IRQ_ASYS_END,
51};
52
53enum audio_base_clock {
54	MT2701_INFRA_SYS_AUDIO,
55	MT2701_TOP_AUD_MCLK_SRC0,
56	MT2701_TOP_AUD_MCLK_SRC1,
57	MT2701_TOP_AUD_A1SYS,
58	MT2701_TOP_AUD_A2SYS,
59	MT2701_AUDSYS_AFE,
60	MT2701_AUDSYS_AFE_CONN,
61	MT2701_AUDSYS_A1SYS,
62	MT2701_AUDSYS_A2SYS,
63	MT2701_BASE_CLK_NUM,
64};
65
66struct mt2701_i2s_data {
67	int i2s_ctrl_reg;
68	int i2s_asrc_fs_shift;
69	int i2s_asrc_fs_mask;
70};
71
72struct mt2701_i2s_path {
73	int mclk_rate;
74	int on[MTK_STREAM_NUM];
75	int occupied[MTK_STREAM_NUM];
76	const struct mt2701_i2s_data *i2s_data[MTK_STREAM_NUM];
77	struct clk *hop_ck[MTK_STREAM_NUM];
78	struct clk *sel_ck;
79	struct clk *div_ck;
80	struct clk *mclk_ck;
81	struct clk *asrco_ck;
82};
83
84struct mt2701_soc_variants {
85	bool has_one_heart_mode;
86	int i2s_num;
87};
88
89struct mt2701_afe_private {
90	struct mt2701_i2s_path *i2s_path;
91	struct clk *base_ck[MT2701_BASE_CLK_NUM];
92	struct clk *mrgif_ck;
93	bool mrg_enable[MTK_STREAM_NUM];
94
95	const struct mt2701_soc_variants *soc;
96};
97
98#endif
99