1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * 4 * Copyright (C) 2012 John Crispin <john@phrozen.org> 5 * Copyright (C) 2012 Lantiq GmbH 6 */ 7 8#include <linux/interrupt.h> 9#include <linux/ioport.h> 10#include <linux/init.h> 11#include <linux/mod_devicetable.h> 12#include <linux/of_irq.h> 13#include <linux/platform_device.h> 14 15#include <lantiq_soc.h> 16#include "../clk.h" 17 18/* the magic ID byte of the core */ 19#define GPTU_MAGIC 0x59 20/* clock control register */ 21#define GPTU_CLC 0x00 22/* id register */ 23#define GPTU_ID 0x08 24/* interrupt node enable */ 25#define GPTU_IRNEN 0xf4 26/* interrupt control register */ 27#define GPTU_IRCR 0xf8 28/* interrupt capture register */ 29#define GPTU_IRNCR 0xfc 30/* there are 3 identical blocks of 2 timers. calculate register offsets */ 31#define GPTU_SHIFT(x) (x % 2 ? 4 : 0) 32#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10) 33/* timer control register */ 34#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00) 35/* timer auto reload register */ 36#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08) 37/* timer manual reload register */ 38#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10) 39/* timer count register */ 40#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18) 41 42/* GPTU_CON(x) */ 43#define CON_CNT BIT(2) 44#define CON_EDGE_ANY (BIT(7) | BIT(6)) 45#define CON_SYNC BIT(8) 46#define CON_CLK_INT BIT(10) 47 48/* GPTU_RUN(x) */ 49#define RUN_SEN BIT(0) 50#define RUN_RL BIT(2) 51 52/* set clock to runmode */ 53#define CLC_RMC BIT(8) 54/* bring core out of suspend */ 55#define CLC_SUSPEND BIT(4) 56/* the disable bit */ 57#define CLC_DISABLE BIT(0) 58 59#define gptu_w32(x, y) ltq_w32((x), gptu_membase + (y)) 60#define gptu_r32(x) ltq_r32(gptu_membase + (x)) 61 62enum gptu_timer { 63 TIMER1A = 0, 64 TIMER1B, 65 TIMER2A, 66 TIMER2B, 67 TIMER3A, 68 TIMER3B 69}; 70 71static void __iomem *gptu_membase; 72static struct resource irqres[6]; 73 74static irqreturn_t timer_irq_handler(int irq, void *priv) 75{ 76 int timer = irq - irqres[0].start; 77 gptu_w32(1 << timer, GPTU_IRNCR); 78 return IRQ_HANDLED; 79} 80 81static void gptu_hwinit(void) 82{ 83 gptu_w32(0x00, GPTU_IRNEN); 84 gptu_w32(0xff, GPTU_IRNCR); 85 gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC); 86} 87 88static void gptu_hwexit(void) 89{ 90 gptu_w32(0x00, GPTU_IRNEN); 91 gptu_w32(0xff, GPTU_IRNCR); 92 gptu_w32(CLC_DISABLE, GPTU_CLC); 93} 94 95static int gptu_enable(struct clk *clk) 96{ 97 int ret = request_irq(irqres[clk->bits].start, timer_irq_handler, 98 IRQF_TIMER, "gtpu", NULL); 99 if (ret) { 100 pr_err("gptu: failed to request irq\n"); 101 return ret; 102 } 103 104 gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT, 105 GPTU_CON(clk->bits)); 106 gptu_w32(1, GPTU_RLD(clk->bits)); 107 gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN); 108 gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); 109 return 0; 110} 111 112static void gptu_disable(struct clk *clk) 113{ 114 gptu_w32(0, GPTU_RUN(clk->bits)); 115 gptu_w32(0, GPTU_CON(clk->bits)); 116 gptu_w32(0, GPTU_RLD(clk->bits)); 117 gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN); 118 free_irq(irqres[clk->bits].start, NULL); 119} 120 121static inline void clkdev_add_gptu(struct device *dev, const char *con, 122 unsigned int timer) 123{ 124 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 125 126 if (!clk) 127 return; 128 clk->cl.dev_id = dev_name(dev); 129 clk->cl.con_id = con; 130 clk->cl.clk = clk; 131 clk->enable = gptu_enable; 132 clk->disable = gptu_disable; 133 clk->bits = timer; 134 clkdev_add(&clk->cl); 135} 136 137static int gptu_probe(struct platform_device *pdev) 138{ 139 struct clk *clk; 140 141 if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 6) != 6) { 142 dev_err(&pdev->dev, "Failed to get IRQ list\n"); 143 return -EINVAL; 144 } 145 146 /* remap gptu register range */ 147 gptu_membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 148 if (IS_ERR(gptu_membase)) 149 return PTR_ERR(gptu_membase); 150 151 /* enable our clock */ 152 clk = clk_get(&pdev->dev, NULL); 153 if (IS_ERR(clk)) { 154 dev_err(&pdev->dev, "Failed to get clock\n"); 155 return -ENOENT; 156 } 157 clk_enable(clk); 158 159 /* power up the core */ 160 gptu_hwinit(); 161 162 /* the gptu has a ID register */ 163 if (((gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) { 164 dev_err(&pdev->dev, "Failed to find magic\n"); 165 gptu_hwexit(); 166 clk_disable(clk); 167 clk_put(clk); 168 return -ENAVAIL; 169 } 170 171 /* register the clocks */ 172 clkdev_add_gptu(&pdev->dev, "timer1a", TIMER1A); 173 clkdev_add_gptu(&pdev->dev, "timer1b", TIMER1B); 174 clkdev_add_gptu(&pdev->dev, "timer2a", TIMER2A); 175 clkdev_add_gptu(&pdev->dev, "timer2b", TIMER2B); 176 clkdev_add_gptu(&pdev->dev, "timer3a", TIMER3A); 177 clkdev_add_gptu(&pdev->dev, "timer3b", TIMER3B); 178 179 dev_info(&pdev->dev, "gptu: 6 timers loaded\n"); 180 181 return 0; 182} 183 184static const struct of_device_id gptu_match[] = { 185 { .compatible = "lantiq,gptu-xway" }, 186 {}, 187}; 188 189static struct platform_driver dma_driver = { 190 .probe = gptu_probe, 191 .driver = { 192 .name = "gptu-xway", 193 .of_match_table = gptu_match, 194 }, 195}; 196 197int __init gptu_init(void) 198{ 199 int ret = platform_driver_register(&dma_driver); 200 201 if (ret) 202 pr_info("gptu: Error registering platform driver\n"); 203 return ret; 204} 205 206arch_initcall(gptu_init); 207