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68a14a56 |
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16-Aug-2019 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
clk: tegra: clk-super: Fix to enable PLLP branches to CPU This patch has a fix to enable PLLP branches to CPU before changing the CPU cluster clock source to PLLP for Gen5 Super clock and disables PLLP branches to CPU when not in use. During system suspend entry and exit, CPU source will be switched to PLLP and this needs PLLP branches to be enabled to CPU prior to the switch. On system resume, warmboot code enables PLLP branches to CPU and powers up the CPU with PLLP clock source. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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9952f691 |
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28-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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2dcabf05 |
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10-Jan-2018 |
Dmitry Osipenko <digetx@gmail.com> |
clk: tegra: Mark HCLK, SCLK and EMC as critical Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks as critical. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: <stable@vger.kernel.org> # v4.16 Signed-off-by: Thierry Reding <treding@nvidia.com>
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109eba2e |
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22-Oct-2017 |
Jon Hunter <jonathanh@nvidia.com> |
clk: tegra: Mark APB clock as critical Currently, the APB clock is registered with the CLK_IGNORE_UNUSED flag to prevent the clock from being disabled if unused on boot. However, even if it is used, it still needs to be always kept enabled so that it doesn't get inadvertently disabled when all of its children are, and so update the flag for the APB clock to be CLK_IS_CRITICAL. Suggested-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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ac99afe5 |
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25-Jul-2017 |
Alex Frid <afrid@nvidia.com> |
clk: tegra: Re-factor T210 PLLX registration Tegra210 PLLX uses the same sequences than then PLLC instances. So there is no need to have a special registration function and ops struct for it. Simplify the code by changing all references to the Tegra210 PLLX registration function to the Tegra210 PLLC registration function and avoid duplicate functionality. Based on work by Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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5a1d5eff |
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04-Dec-2015 |
Jon Hunter <jonathanh@nvidia.com> |
clk: tegra: super: Fix sparse warnings for functions not declared as static Sparse reports the following warnings for structures and functions that should be declared static: drivers/clk/tegra/clk-tegra-super-gen4.c:70:35: warning: symbol 'tegra_super_gen_info_gen4' was not declared. Should it be static? drivers/clk/tegra/clk-tegra-super-gen4.c:96:35: warning: symbol 'tegra_super_gen_info_gen5' was not declared. Should it be static? drivers/clk/tegra/clk-tegra-super-gen4.c:174:13: warning: symbol 'tegra_super_clk_init' was not declared. Should it be static? Fix this by making the above static. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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139fd309 |
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18-Jun-2015 |
Bill Huang <bilhuang@nvidia.com> |
clk: tegra: Add Super Gen5 Logic Super clock divider control and clock source mux of Tegra210 has changed a little against prior SoCs, this patch adds Gen5 logic to address those differences. Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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584ac4e9 |
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19-Jun-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: tegra: Properly include clk.h Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. Also add in a clkdev.h include that was missing in a file using clkdev APIs. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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79cf95c7 |
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13-May-2015 |
Tuomas Tynkkynen <ttynkkynen@nvidia.com> |
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock The DFLL clocksource was missing from the list of possible parents for the fast CPU cluster. Add it to the list. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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88b4bd70 |
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26-Dec-2013 |
Andrew Bresticker <abrestic@chromium.org> |
clk: tegra: cclk_lp has a pllx/2 divider When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
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a7c8485a |
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03-Sep-2013 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
clk: tegra: introduce common gen4 super clock Introduce a common function which performs super clock initialization for Tegra114 and beyond. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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