1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (c) 2013, The Linux Foundation. All rights reserved. */ 3 4#ifndef __QCOM_CLK_BRANCH_H__ 5#define __QCOM_CLK_BRANCH_H__ 6 7#include <linux/bitfield.h> 8#include <linux/clk-provider.h> 9 10#include "clk-regmap.h" 11 12/** 13 * struct clk_branch - gating clock with status bit and dynamic hardware gating 14 * 15 * @hwcg_reg: dynamic hardware clock gating register 16 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating 17 * @halt_reg: halt register 18 * @halt_bit: ANDed with @halt_reg to test for clock halted 19 * @halt_check: type of halt checking to perform 20 * @clkr: handle between common and hardware-specific interfaces 21 * 22 * Clock which can gate its output. 23 */ 24struct clk_branch { 25 u32 hwcg_reg; 26 u32 halt_reg; 27 u8 hwcg_bit; 28 u8 halt_bit; 29 u8 halt_check; 30#define BRANCH_VOTED BIT(7) /* Delay on disable */ 31#define BRANCH_HALT 0 /* pol: 1 = halt */ 32#define BRANCH_HALT_VOTED (BRANCH_HALT | BRANCH_VOTED) 33#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */ 34#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED) 35#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */ 36#define BRANCH_HALT_SKIP 3 /* Don't check halt bit */ 37 38 struct clk_regmap clkr; 39}; 40 41/** 42 * struct clk_mem_branch - gating clock which are associated with memories 43 * 44 * @mem_enable_reg: branch clock memory gating register 45 * @mem_ack_reg: branch clock memory ack register 46 * @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg 47 * @branch: branch clock gating handle 48 * 49 * Clock which can gate its memories. 50 */ 51struct clk_mem_branch { 52 u32 mem_enable_reg; 53 u32 mem_ack_reg; 54 u32 mem_enable_ack_mask; 55 struct clk_branch branch; 56}; 57 58/* Branch clock common bits for HLOS-owned clocks */ 59#define CBCR_CLK_OFF BIT(31) 60#define CBCR_NOC_FSM_STATUS GENMASK(30, 28) 61 #define FSM_STATUS_ON BIT(1) 62#define CBCR_FORCE_MEM_CORE_ON BIT(14) 63#define CBCR_FORCE_MEM_PERIPH_ON BIT(13) 64#define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) 65#define CBCR_WAKEUP GENMASK(11, 8) 66#define CBCR_SLEEP GENMASK(7, 4) 67#define CBCR_CLOCK_ENABLE BIT(0) 68 69static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, 70 struct clk_branch clk, bool on) 71{ 72 regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_CORE_ON, 73 on ? CBCR_FORCE_MEM_CORE_ON : 0); 74} 75 76static inline void qcom_branch_set_force_periph_on(struct regmap *regmap, 77 struct clk_branch clk, bool on) 78{ 79 regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_ON, 80 on ? CBCR_FORCE_MEM_PERIPH_ON : 0); 81} 82 83static inline void qcom_branch_set_force_periph_off(struct regmap *regmap, 84 struct clk_branch clk, bool on) 85{ 86 regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_OFF, 87 on ? CBCR_FORCE_MEM_PERIPH_OFF : 0); 88} 89 90static inline void qcom_branch_set_wakeup(struct regmap *regmap, struct clk_branch clk, u32 val) 91{ 92 regmap_update_bits(regmap, clk.halt_reg, CBCR_WAKEUP, 93 FIELD_PREP(CBCR_WAKEUP, val)); 94} 95 96static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branch clk, u32 val) 97{ 98 regmap_update_bits(regmap, clk.halt_reg, CBCR_SLEEP, 99 FIELD_PREP(CBCR_SLEEP, val)); 100} 101 102static inline void qcom_branch_set_clk_en(struct regmap *regmap, u32 cbcr) 103{ 104 regmap_update_bits(regmap, cbcr, CBCR_CLOCK_ENABLE, CBCR_CLOCK_ENABLE); 105} 106 107extern const struct clk_ops clk_branch_ops; 108extern const struct clk_ops clk_branch2_ops; 109extern const struct clk_ops clk_branch_simple_ops; 110extern const struct clk_ops clk_branch2_aon_ops; 111extern const struct clk_ops clk_branch2_mem_ops; 112 113#define to_clk_branch(_hw) \ 114 container_of(to_clk_regmap(_hw), struct clk_branch, clkr) 115 116#define to_clk_mem_branch(_hw) \ 117 container_of(to_clk_branch(_hw), struct clk_mem_branch, branch) 118 119#endif 120