/linux-master/drivers/pci/ |
H A D | pci-acpi.c | 502 u32 match_reg, write_reg, header, orig_value; local 544 pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg); 545 orig_value = write_reg; 546 write_reg &= reg->reg_mask_and; 547 write_reg |= reg->reg_mask_or; 549 if (orig_value == write_reg) 552 pci_write_config_dword(dev, pos + reg->reg_offset, write_reg); 555 pos, orig_value, write_reg);
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/linux-master/drivers/rtc/ |
H A D | rtc-r9701.c | 40 static int write_reg(struct device *dev, int address, unsigned char data) function 93 ret = write_reg(dev, RHRCNT, bin2bcd(dt->tm_hour)); 94 ret = ret ? ret : write_reg(dev, RMINCNT, bin2bcd(dt->tm_min)); 95 ret = ret ? ret : write_reg(dev, RSECCNT, bin2bcd(dt->tm_sec)); 96 ret = ret ? ret : write_reg(dev, RDAYCNT, bin2bcd(dt->tm_mday)); 97 ret = ret ? ret : write_reg(dev, RMONCNT, bin2bcd(dt->tm_mon + 1)); 98 ret = ret ? ret : write_reg(dev, RYRCNT, bin2bcd(dt->tm_year - 100));
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/linux-master/drivers/staging/fbtft/ |
H A D | fb_agm1264k-fl.c | 71 write_reg(par, i, 0x3f); /* display on */ 72 write_reg(par, i, 0x40); /* set x to 0 */ 73 write_reg(par, i, 0xb0); /* set page to 0 */ 74 write_reg(par, i, 0xc0); /* set start line to 0 */ 350 write_reg(par, 0x00, BIT(6) | (u8)addr_win.xs); 351 write_reg(par, 0x00, (0x17 << 3) | (u8)y); 373 write_reg(par, 0x01, BIT(6)); 374 write_reg(par, 0x01, (0x17 << 3) | (u8)y);
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H A D | fb_bd663474.c | 31 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ 35 write_reg(par, 0x100, 0x0000); /* power supply setup */ 36 write_reg(par, 0x101, 0x0000); 37 write_reg(par, 0x102, 0x3110); 38 write_reg(par, 0x103, 0xe200); 39 write_reg(par, 0x110, 0x009d); 40 write_reg(par, 0x111, 0x0022); 41 write_reg(par, 0x100, 0x0120); 44 write_reg(par, 0x100, 0x3120); 47 write_reg(pa [all...] |
H A D | fb_hx8340bn.c | 45 write_reg(par, 0xC1, 0xFF, 0x83, 0x40); 53 write_reg(par, 0x11); 57 write_reg(par, 0xCA, 0x70, 0x00, 0xD9); 65 write_reg(par, 0xB0, 0x01, 0x11); 68 write_reg(par, 0xC9, 0x90, 0x49, 0x10, 0x28, 0x28, 0x10, 0x00, 0x06); 78 write_reg(par, 0xB5, 0x35, 0x20, 0x45); 87 write_reg(par, 0xB4, 0x33, 0x25, 0x4C); 96 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); 103 write_reg(par, MIPI_DCS_SET_DISPLAY_ON); 111 write_reg(pa [all...] |
H A D | fb_hx8347d.c | 28 write_reg(par, 0xEA, 0x00); 29 write_reg(par, 0xEB, 0x20); 30 write_reg(par, 0xEC, 0x0C); 31 write_reg(par, 0xED, 0xC4); 32 write_reg(par, 0xE8, 0x40); 33 write_reg(par, 0xE9, 0x38); 34 write_reg(par, 0xF1, 0x01); 35 write_reg(par, 0xF2, 0x10); 36 write_reg(par, 0x27, 0xA3); 39 write_reg(pa [all...] |
H A D | fb_ili9163.c | 79 write_reg(par, MIPI_DCS_SOFT_RESET); /* software reset */ 81 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); /* exit sleep */ 83 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); 85 write_reg(par, MIPI_DCS_SET_GAMMA_CURVE, 0x02); 87 write_reg(par, CMD_GAMRSEL, 0x01); /* Enable Gamma adj */ 89 write_reg(par, MIPI_DCS_ENTER_NORMAL_MODE); 90 write_reg(par, CMD_DFUNCTR, 0xff, 0x06); 92 write_reg(par, CMD_FRMCTR1, 0x08, 0x02); 93 write_reg(par, CMD_DINVCTR, 0x07); /* display inversion */ 95 write_reg(pa [all...] |
H A D | fb_ili9320.c | 26 write_reg(par, 0x0000); 49 write_reg(par, 0x00E5, 0x8000); 52 write_reg(par, 0x0000, 0x0001); 55 write_reg(par, 0x0001, 0x0100); 58 write_reg(par, 0x0002, 0x0700); 61 write_reg(par, 0x0004, 0x0000); 64 write_reg(par, 0x0008, 0x0202); 67 write_reg(par, 0x0009, 0x0000); 70 write_reg(par, 0x000A, 0x0000); 73 write_reg(pa [all...] |
H A D | fb_ili9325.c | 96 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ 97 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ 98 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ 99 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ 100 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ 101 write_reg(par, 0x0004, 0x0000); /* Resize register */ 102 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ 103 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ 104 write_reg(par, 0x000A, 0x0000); /* FMARK function */ 105 write_reg(pa [all...] |
H A D | fb_ili9340.c | 25 write_reg(par, 0xEF, 0x03, 0x80, 0x02); 26 write_reg(par, 0xCF, 0x00, 0XC1, 0X30); 27 write_reg(par, 0xED, 0x64, 0x03, 0X12, 0X81); 28 write_reg(par, 0xE8, 0x85, 0x00, 0x78); 29 write_reg(par, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02); 30 write_reg(par, 0xF7, 0x20); 31 write_reg(par, 0xEA, 0x00, 0x00); 34 write_reg(par, 0xC0, 0x23); 37 write_reg(par, 0xC1, 0x10); 40 write_reg(pa [all...] |
H A D | fb_ili9341.c | 34 write_reg(par, MIPI_DCS_SOFT_RESET); 36 write_reg(par, MIPI_DCS_SET_DISPLAY_OFF); 38 write_reg(par, 0xCF, 0x00, 0x83, 0x30); 39 write_reg(par, 0xED, 0x64, 0x03, 0x12, 0x81); 40 write_reg(par, 0xE8, 0x85, 0x01, 0x79); 41 write_reg(par, 0xCB, 0x39, 0X2C, 0x00, 0x34, 0x02); 42 write_reg(par, 0xF7, 0x20); 43 write_reg(par, 0xEA, 0x00, 0x00); 45 write_reg(par, 0xC0, 0x26); 46 write_reg(pa [all...] |
H A D | fb_pcd8544.c | 45 write_reg(par, 0x21); 53 write_reg(par, 0x04 | (tc & 0x3)); 63 write_reg(par, 0x10 | (bs & 0x7)); 72 write_reg(par, 0x22); 81 write_reg(par, 0x08 | 4); 93 write_reg(par, 0x80); 101 write_reg(par, 0x40); 136 write_reg(par, 0x23); /* turn on extended instruction set */ 137 write_reg(par, 0x80 | curves[0]); 138 write_reg(pa [all...] |
H A D | fb_s6d1121.c | 33 write_reg(par, 0x0011, 0x2004); 34 write_reg(par, 0x0013, 0xCC00); 35 write_reg(par, 0x0015, 0x2600); 36 write_reg(par, 0x0014, 0x252A); 37 write_reg(par, 0x0012, 0x0033); 38 write_reg(par, 0x0013, 0xCC04); 39 write_reg(par, 0x0013, 0xCC06); 40 write_reg(par, 0x0013, 0xCC4F); 41 write_reg(par, 0x0013, 0x674F); 42 write_reg(pa [all...] |
H A D | fb_seps525.c | 104 write_reg(par, SEPS525_REDUCE_CURRENT, 0x03); 107 write_reg(par, SEPS525_REDUCE_CURRENT, 0x00); 110 write_reg(par, SEPS525_SCREEN_SAVER_CONTEROL, 0x00); 112 write_reg(par, SEPS525_OSC_CTL, 0x01); 114 write_reg(par, SEPS525_CLOCK_DIV, 0x90); 116 write_reg(par, SEPS525_IREF, 0x01); 119 write_reg(par, SEPS525_PRECHARGE_TIME_R, 0x04); 120 write_reg(par, SEPS525_PRECHARGE_TIME_G, 0x05); 121 write_reg(par, SEPS525_PRECHARGE_TIME_B, 0x05); 124 write_reg(pa [all...] |
H A D | fb_sh1106.c | 38 write_reg(par, 0xAE); 41 write_reg(par, 0xD5, 0x80); 44 write_reg(par, 0xA8, par->info->var.yres - 1); 47 write_reg(par, 0xD3, 0x00); 50 write_reg(par, 0x40 | 0x0); 54 write_reg(par, 0xA0 | 0x1); 58 write_reg(par, 0xC8); 63 write_reg(par, 0xDA, 0x12); 66 write_reg(par, 0xDA, 0x12); 69 write_reg(pa [all...] |
H A D | fb_ssd1289.c | 30 write_reg(par, 0x00, 0x0001); 31 write_reg(par, 0x03, 0xA8A4); 32 write_reg(par, 0x0C, 0x0000); 33 write_reg(par, 0x0D, 0x080C); 34 write_reg(par, 0x0E, 0x2B00); 35 write_reg(par, 0x1E, 0x00B7); 36 write_reg(par, 0x01, 38 write_reg(par, 0x02, 0x0600); 39 write_reg(par, 0x10, 0x0000); 40 write_reg(pa [all...] |
H A D | fb_ssd1325.c | 23 * write_reg() caveat: 26 * write_reg(par, val1, val2); 29 * write_reg(par, val1); 30 * write_reg(par, val2); 38 write_reg(par, 0xb3); 39 write_reg(par, 0xf0); 40 write_reg(par, 0xae); 41 write_reg(par, 0xa1); 42 write_reg(par, 0x00); 43 write_reg(pa [all...] |
H A D | fb_ssd1331.c | 29 write_reg(par, 0xae); /* Display Off */ 33 write_reg(par, 0xa0, 0x60 | (par->bgr << 2)); 35 write_reg(par, 0xa0, 0x72 | (par->bgr << 2)); 37 write_reg(par, 0x72); /* RGB colour */ 38 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ 39 write_reg(par, 0xa2, 0x00); /* Set Display Offset */ 40 write_reg(par, 0xa4); /* NORMALDISPLAY */ 41 write_reg(par, 0xa8, 0x3f); /* Set multiplex */ 42 write_reg(par, 0xad, 0x8e); /* Set master */ 43 /* write_reg(pa [all...] |
H A D | fb_ssd1351.c | 38 write_reg(par, 0xfd, 0x12); /* Command Lock */ 39 write_reg(par, 0xfd, 0xb1); /* Command Lock */ 40 write_reg(par, 0xae); /* Display Off */ 41 write_reg(par, 0xb3, 0xf1); /* Front Clock Div */ 42 write_reg(par, 0xca, 0x7f); /* Set Mux Ratio */ 43 write_reg(par, 0x15, 0x00, 0x7f); /* Set Column Address */ 44 write_reg(par, 0x75, 0x00, 0x7f); /* Set Row Address */ 45 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ 46 write_reg(par, 0xa2, 0x00); /* Set Display Offset */ 47 write_reg(pa [all...] |
H A D | fb_st7789v.c | 154 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); 158 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); 160 write_reg(par, PORCTRL, 0x05, 0x05, 0x00, 0x33, 0x33); 163 write_reg(par, PORCTRL, 0x08, 0x08, 0x00, 0x22, 0x22); 170 write_reg(par, GCTRL, 0x75); 172 write_reg(par, GCTRL, 0x35); 178 write_reg(par, VDVVRHEN, 0x01, 0xFF); 185 write_reg(par, VRHS, 0x13); 187 write_reg(par, VRHS, 0x0B); 190 write_reg(pa [all...] |
H A D | fb_uc1611.c | 81 write_reg(par, 0xE2); 84 write_reg(par, 0xE8 | (ratio & 0x03)); 87 write_reg(par, 0x81); 88 write_reg(par, (gain & 0x03) << 6 | (pot & 0x3F)); 91 write_reg(par, 0x24 | (temp & 0x03)); 94 write_reg(par, 0x28 | (load & 0x03)); 97 write_reg(par, 0x2C | (pump & 0x03)); 100 write_reg(par, 0xA6 | 0x01); 103 write_reg(par, 0xD0 | (0x02 & 0x03)); 106 write_reg(pa [all...] |
H A D | fb_upd161704.c | 31 write_reg(par, 0x0003, 0x0001); /* Soft reset */ 34 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ 38 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ 40 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ 41 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ 43 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ 44 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */ 46 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */ 47 write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */ 49 write_reg(pa [all...] |
H A D | fbtft-core.c | 205 write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS, 208 write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, 211 write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
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H A D | fbtft.h | 40 * @write_reg: Writes to controller register 236 #define write_reg(par, ...) \ macro
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/linux-master/drivers/video/fbdev/ |
H A D | broadsheetfb.c | 1066 par->write_reg = broadsheet_write_reg;
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