/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 546 const TargetRegisterClass *RC = local 548 if (!RC) 553 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) || 554 SystemZ::GR32BitRegClass.hasSubClassEq(RC) || 555 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { 573 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); local 580 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) { 595 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { 873 bool isKill, int FrameIdx, const TargetRegisterClass *RC, 880 getLoadStoreOpcodes(RC, LoadOpcod 871 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 886 loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 1466 getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegAllocFast.cpp | 256 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local 257 unsigned Size = TRI->getSpillSize(RC); 258 unsigned Align = TRI->getSpillAlignment(RC); 322 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local 323 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI); 348 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local 349 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI); 668 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local 670 << " in class " << TRI->getRegClassName(&RC) 675 RC 762 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); local [all...] |
H A D | CriticalAntiDepBreaker.cpp | 405 const TargetRegisterClass *RC, 407 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); 639 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] local 641 assert((AntiDepReg == 0 || RC != nullptr) && 643 if (RC == reinterpret_cast<TargetRegisterClass *>(-1)) 657 RC, ForbidRegs)) { 401 findSuitableFreeRegister(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, const TargetRegisterClass *RC, SmallVectorImpl<unsigned> &Forbid) argument
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H A D | PeepholeOptimizer.cpp | 211 RecurrenceCycle &RC); 571 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); local 585 Register NewVR = MRI->createVirtualRegister(RC); 1496 RecurrenceCycle &RC) { 1510 if (RC.size() >= MaxRecurrenceChain) 1533 RC.push_back(RecurrenceInstr(&MI)); 1534 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC); 1539 RC.push_back(RecurrenceInstr(&MI, Idx, CommIdx)); 1540 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC); 1574 RecurrenceCycle RC; local 1494 findTargetRecurrence( unsigned Reg, const SmallSet<unsigned, 2> &TargetRegs, RecurrenceCycle &RC) argument [all...] |
H A D | AggressiveAntiDepBreaker.h | 48 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::RegisterReference
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H A D | ModuloSchedule.cpp | 548 const TargetRegisterClass *RC = MRI.getRegClass(Def); local 549 NewReg = MRI.createVirtualRegister(RC); 664 const TargetRegisterClass *RC = MRI.getRegClass(Def); local 665 Register NewReg = MRI.createVirtualRegister(RC); 1033 const TargetRegisterClass *RC = MRI.getRegClass(reg); local 1034 Register NewReg = MRI.createVirtualRegister(RC); 1269 const TargetRegisterClass *RC = nullptr); 1271 Register undef(const TargetRegisterClass *RC); 1436 auto RC = MRI.getRegClass(Reg); local 1437 Register R = MRI.createVirtualRegister(RC); 1449 phi(Register LoopReg, Optional<Register> InitReg, const TargetRegisterClass *RC) argument 1499 undef(const TargetRegisterClass *RC) argument 1625 auto RC = MRI.getRegClass(PhiR); local 1841 auto RC = MRI.getRegClass(MI.getOperand(0).getReg()); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 132 const TargetRegisterClass *RC); 179 const TargetRegisterClass *RC, unsigned Op0, 468 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local 470 ResultReg = createResultReg(RC); 771 const TargetRegisterClass *RC = nullptr; local 782 RC = &X86::GR64RegClass; 788 RC = &X86::GR32RegClass; 791 LoadReg = createResultReg(RC); 1782 const TargetRegisterClass *RC = nullptr; local 1785 RC 1866 const TargetRegisterClass *RC; member in struct:DivRemEntry 2025 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2200 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2352 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2380 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2450 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); local 2469 X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned TargetOpc, const TargetRegisterClass *RC) argument 2626 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); local 2681 const TargetRegisterClass *RC = nullptr; local 2838 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local 3133 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local 3885 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL)); local 3975 fastEmitInst_rrrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill, unsigned Op3, bool Op3IsKill) argument [all...] |
H A D | X86DomainReassignment.cpp | 44 static bool isGPR(const TargetRegisterClass *RC) { argument 45 return X86::GR64RegClass.hasSubClassEq(RC) || 46 X86::GR32RegClass.hasSubClassEq(RC) || 47 X86::GR16RegClass.hasSubClassEq(RC) || 48 X86::GR8RegClass.hasSubClassEq(RC); 51 static bool isMask(const TargetRegisterClass *RC, argument 53 return X86::VK16RegClass.hasSubClassEq(RC); 56 static RegDomain getDomain(const TargetRegisterClass *RC, argument 58 if (isGPR(RC)) 60 if (isMask(RC, TR [all...] |
H A D | X86SpeculativeLoadHardening.cpp | 154 const TargetRegisterClass *RC; member in struct:__anon2518::X86SpeculativeLoadHardeningPass::PredState 157 PredState(MachineFunction &MF, const TargetRegisterClass *RC) argument 158 : RC(RC), SSA(MF) {} 446 PS->PoisonReg = MRI->createVirtualRegister(PS->RC); 479 PS->InitialReg = MRI->createVirtualRegister(PS->RC); 750 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; 753 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC); 1176 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; 1178 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC); 2238 auto *RC = MRI->getRegClass(Reg); local 2286 auto *RC = MRI->getRegClass(Reg); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 309 for (CodeGenRegisterClass &RC : RegClasses) { 311 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 366 for (const auto &RC : getRegBank().getRegClasses()) { 367 if (RC.contains(Reg)) { 368 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 381 for (const auto &RC : getRegBank().getRegClasses()) 382 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end()); 577 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { argument 578 std::vector<Record*> Defs = RC [all...] |
H A D | CodeGenIntrinsics.h | 181 explicit CodeGenIntrinsicTable(const RecordKeeper &RC);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRInstrInfo.cpp | 124 const TargetRegisterClass *RC, 144 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) { 146 } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) { 162 const TargetRegisterClass *RC, 178 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) { 180 } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) { 120 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 159 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | GCNRegPressure.cpp | 88 const auto RC = MRI.getRegClass(Reg); local 90 return STI->isSGPRClass(RC) ? 91 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) : 92 STI->hasAGPRs(RC) ? 93 (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) : 94 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
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H A D | AMDGPUISelLowering.h | 278 const TargetRegisterClass *RC, 283 const TargetRegisterClass *RC, 285 return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode())); 290 const TargetRegisterClass *RC, 292 return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true); 309 const TargetRegisterClass *RC, 282 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument 289 CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
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H A D | R600RegisterInfo.cpp | 91 const TargetRegisterClass *RC) const {
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H A D | AMDGPUInstructionSelector.cpp | 79 const TargetRegisterClass *RC = local 81 if (RC) { 83 return RC->hasSuperClassEq(TRI.getBoolRC()) && 103 const TargetRegisterClass *RC local 105 if (!RC) 107 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); 139 const TargetRegisterClass *RC = local 141 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) 164 const TargetRegisterClass *RC local 260 const TargetRegisterClass *RC = TRI.getBoolRC(); local 337 const TargetRegisterClass &RC local 475 const TargetRegisterClass *RC = local 575 const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, *MRI); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | GuardWidening.cpp | 551 for (auto &RC : CombinedChecks) { 552 makeAvailableAt(RC.getCheckInst(), InsertPt); 554 Result = BinaryOperator::CreateAnd(RC.getCheckInst(), Result, "", 557 Result = RC.getCheckInst(); 664 auto IsCurrentCheck = [&](GuardWideningImpl::RangeCheck &RC) { 665 return RC.getBase() == CurrentBase && RC.getLength() == CurrentLength; 699 auto OffsetOK = [&](const GuardWideningImpl::RangeCheck &RC) { 700 return (HighOffset - RC.getOffsetValue()).ult(MaxDiff);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16RegisterInfo.cpp | 60 const TargetRegisterClass *RC, 56 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument
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H A D | MipsRegisterBankInfo.h | 35 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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H A D | MipsRegisterInfo.cpp | 67 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument 69 switch (RC->getID()) {
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | VirtRegMap.h | 64 /// createSpillSlot - Allocate a spill slot for RC from MFI. 65 unsigned createSpillSlot(const TargetRegisterClass *RC);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 2034 unsigned FastISel::createResultReg(const TargetRegisterClass *RC) { argument 2035 return MRI.createVirtualRegister(RC); 2056 const TargetRegisterClass *RC) { 2057 unsigned ResultReg = createResultReg(RC); 2065 const TargetRegisterClass *RC, unsigned Op0, 2069 unsigned ResultReg = createResultReg(RC); 2086 const TargetRegisterClass *RC, unsigned Op0, 2091 unsigned ResultReg = createResultReg(RC); 2110 const TargetRegisterClass *RC, unsigned Op0, 2116 unsigned ResultReg = createResultReg(RC); 2055 fastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass *RC) argument 2064 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 2085 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 2109 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 2137 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 2159 fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument 2184 fastEmitInst_f(unsigned MachineInstOpcode, const TargetRegisterClass *RC, const ConstantFP *FPImm) argument 2203 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 2229 fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument 2250 const TargetRegisterClass *RC = MRI.getRegClass(Op0); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 155 const TargetRegisterClass *RC, unsigned AltName, 616 // Prints the register in MO using class RC using the offset in the 620 const TargetRegisterClass *RC, 625 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg)); 665 const TargetRegisterClass *RC; local 668 RC = &AArch64::FPR8RegClass; 671 RC = &AArch64::FPR16RegClass; 674 RC = &AArch64::FPR32RegClass; 677 RC = &AArch64::FPR64RegClass; 680 RC 619 printAsmRegInClass(const MachineOperand &MO, const TargetRegisterClass *RC, unsigned AltName, raw_ostream &O) argument [all...] |
/freebsd-11-stable/contrib/ntp/scripts/build/ |
H A D | UpdatePoint | 92 # Do we want to change the RC point? (n=no, z=empty rcpoint and zero 99 # if we are not in a beta or RC state, enter beta unless point is NEW. 102 # else if we are in an RC state: 110 # - - bump the RC point 145 # skip all -beta and -RC prereleases to the next point. 187 echo "rcpoint GO is allowed only when prerelease is RC or empty." 192 rc|RC)
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.h | 590 /// Get a register bank that covers \p RC. 592 /// \pre \p RC is a user-defined register class (as opposed as one 595 /// \note The mapping RC -> RegBank could be built while adding the 603 getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const { argument 637 /// Constrain the (possibly generic) virtual register \p Reg to \p RC. 645 constrainGenericRegister(Register Reg, const TargetRegisterClass &RC,
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