1303231Sdim//===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===// 2303231Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6303231Sdim// 7303231Sdim//===----------------------------------------------------------------------===// 8303231Sdim// 9303231Sdim// This file contains the AVR implementation of the TargetInstrInfo class. 10303231Sdim// 11303231Sdim//===----------------------------------------------------------------------===// 12303231Sdim 13303231Sdim#include "AVRInstrInfo.h" 14303231Sdim 15303231Sdim#include "llvm/ADT/STLExtras.h" 16303231Sdim#include "llvm/CodeGen/MachineConstantPool.h" 17303231Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 18303231Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 19303231Sdim#include "llvm/CodeGen/MachineMemOperand.h" 20303231Sdim#include "llvm/IR/Constants.h" 21303231Sdim#include "llvm/IR/Function.h" 22303231Sdim#include "llvm/MC/MCContext.h" 23303231Sdim#include "llvm/Support/Debug.h" 24303231Sdim#include "llvm/Support/ErrorHandling.h" 25303231Sdim#include "llvm/Support/TargetRegistry.h" 26303231Sdim 27303231Sdim#include "AVR.h" 28303231Sdim#include "AVRMachineFunctionInfo.h" 29314564Sdim#include "AVRRegisterInfo.h" 30303231Sdim#include "AVRTargetMachine.h" 31303231Sdim#include "MCTargetDesc/AVRMCTargetDesc.h" 32303231Sdim 33303231Sdim#define GET_INSTRINFO_CTOR_DTOR 34303231Sdim#include "AVRGenInstrInfo.inc" 35303231Sdim 36303231Sdimnamespace llvm { 37303231Sdim 38303231SdimAVRInstrInfo::AVRInstrInfo() 39303231Sdim : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {} 40303231Sdim 41303231Sdimvoid AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 42303231Sdim MachineBasicBlock::iterator MI, 43360784Sdim const DebugLoc &DL, MCRegister DestReg, 44360784Sdim MCRegister SrcReg, bool KillSrc) const { 45314564Sdim const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>(); 46314564Sdim const AVRRegisterInfo &TRI = *STI.getRegisterInfo(); 47303231Sdim unsigned Opc; 48303231Sdim 49314564Sdim // Not all AVR devices support the 16-bit `MOVW` instruction. 50314564Sdim if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { 51314564Sdim if (STI.hasMOVW()) { 52314564Sdim BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg) 53314564Sdim .addReg(SrcReg, getKillRegState(KillSrc)); 54314564Sdim } else { 55314564Sdim unsigned DestLo, DestHi, SrcLo, SrcHi; 56314564Sdim 57314564Sdim TRI.splitReg(DestReg, DestLo, DestHi); 58314564Sdim TRI.splitReg(SrcReg, SrcLo, SrcHi); 59314564Sdim 60314564Sdim // Copy each individual register with the `MOV` instruction. 61314564Sdim BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo) 62314564Sdim .addReg(SrcLo, getKillRegState(KillSrc)); 63314564Sdim BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi) 64314564Sdim .addReg(SrcHi, getKillRegState(KillSrc)); 65314564Sdim } 66303231Sdim } else { 67314564Sdim if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) { 68314564Sdim Opc = AVR::MOVRdRr; 69314564Sdim } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) { 70314564Sdim Opc = AVR::SPREAD; 71314564Sdim } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) { 72314564Sdim Opc = AVR::SPWRITE; 73314564Sdim } else { 74314564Sdim llvm_unreachable("Impossible reg-to-reg copy"); 75314564Sdim } 76314564Sdim 77314564Sdim BuildMI(MBB, MI, DL, get(Opc), DestReg) 78314564Sdim .addReg(SrcReg, getKillRegState(KillSrc)); 79303231Sdim } 80303231Sdim} 81303231Sdim 82303231Sdimunsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 83303231Sdim int &FrameIndex) const { 84303231Sdim switch (MI.getOpcode()) { 85303231Sdim case AVR::LDDRdPtrQ: 86303231Sdim case AVR::LDDWRdYQ: { //:FIXME: remove this once PR13375 gets fixed 87303231Sdim if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && 88303231Sdim MI.getOperand(2).getImm() == 0) { 89303231Sdim FrameIndex = MI.getOperand(1).getIndex(); 90303231Sdim return MI.getOperand(0).getReg(); 91303231Sdim } 92303231Sdim break; 93303231Sdim } 94303231Sdim default: 95303231Sdim break; 96303231Sdim } 97303231Sdim 98303231Sdim return 0; 99303231Sdim} 100303231Sdim 101303231Sdimunsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 102303231Sdim int &FrameIndex) const { 103303231Sdim switch (MI.getOpcode()) { 104303231Sdim case AVR::STDPtrQRr: 105303231Sdim case AVR::STDWPtrQRr: { 106303231Sdim if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() && 107303231Sdim MI.getOperand(1).getImm() == 0) { 108303231Sdim FrameIndex = MI.getOperand(0).getIndex(); 109303231Sdim return MI.getOperand(2).getReg(); 110303231Sdim } 111303231Sdim break; 112303231Sdim } 113303231Sdim default: 114303231Sdim break; 115303231Sdim } 116303231Sdim 117303231Sdim return 0; 118303231Sdim} 119303231Sdim 120303231Sdimvoid AVRInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 121303231Sdim MachineBasicBlock::iterator MI, 122303231Sdim unsigned SrcReg, bool isKill, 123303231Sdim int FrameIndex, 124303231Sdim const TargetRegisterClass *RC, 125303231Sdim const TargetRegisterInfo *TRI) const { 126303231Sdim MachineFunction &MF = *MBB.getParent(); 127314564Sdim AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); 128303231Sdim 129314564Sdim AFI->setHasSpills(true); 130314564Sdim 131303231Sdim DebugLoc DL; 132303231Sdim if (MI != MBB.end()) { 133303231Sdim DL = MI->getDebugLoc(); 134303231Sdim } 135303231Sdim 136314564Sdim const MachineFrameInfo &MFI = MF.getFrameInfo(); 137303231Sdim 138303231Sdim MachineMemOperand *MMO = MF.getMachineMemOperand( 139303231Sdim MachinePointerInfo::getFixedStack(MF, FrameIndex), 140303231Sdim MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex), 141303231Sdim MFI.getObjectAlignment(FrameIndex)); 142303231Sdim 143303231Sdim unsigned Opcode = 0; 144321369Sdim if (TRI->isTypeLegalForClass(*RC, MVT::i8)) { 145303231Sdim Opcode = AVR::STDPtrQRr; 146321369Sdim } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) { 147303231Sdim Opcode = AVR::STDWPtrQRr; 148303231Sdim } else { 149303231Sdim llvm_unreachable("Cannot store this register into a stack slot!"); 150303231Sdim } 151303231Sdim 152303231Sdim BuildMI(MBB, MI, DL, get(Opcode)) 153303231Sdim .addFrameIndex(FrameIndex) 154303231Sdim .addImm(0) 155303231Sdim .addReg(SrcReg, getKillRegState(isKill)) 156303231Sdim .addMemOperand(MMO); 157303231Sdim} 158303231Sdim 159303231Sdimvoid AVRInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 160303231Sdim MachineBasicBlock::iterator MI, 161303231Sdim unsigned DestReg, int FrameIndex, 162303231Sdim const TargetRegisterClass *RC, 163303231Sdim const TargetRegisterInfo *TRI) const { 164303231Sdim DebugLoc DL; 165303231Sdim if (MI != MBB.end()) { 166303231Sdim DL = MI->getDebugLoc(); 167303231Sdim } 168303231Sdim 169303231Sdim MachineFunction &MF = *MBB.getParent(); 170314564Sdim const MachineFrameInfo &MFI = MF.getFrameInfo(); 171303231Sdim 172303231Sdim MachineMemOperand *MMO = MF.getMachineMemOperand( 173303231Sdim MachinePointerInfo::getFixedStack(MF, FrameIndex), 174303231Sdim MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex), 175303231Sdim MFI.getObjectAlignment(FrameIndex)); 176303231Sdim 177303231Sdim unsigned Opcode = 0; 178321369Sdim if (TRI->isTypeLegalForClass(*RC, MVT::i8)) { 179303231Sdim Opcode = AVR::LDDRdPtrQ; 180321369Sdim } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) { 181303231Sdim // Opcode = AVR::LDDWRdPtrQ; 182303231Sdim //:FIXME: remove this once PR13375 gets fixed 183303231Sdim Opcode = AVR::LDDWRdYQ; 184303231Sdim } else { 185303231Sdim llvm_unreachable("Cannot load this register from a stack slot!"); 186303231Sdim } 187303231Sdim 188303231Sdim BuildMI(MBB, MI, DL, get(Opcode), DestReg) 189303231Sdim .addFrameIndex(FrameIndex) 190303231Sdim .addImm(0) 191303231Sdim .addMemOperand(MMO); 192303231Sdim} 193303231Sdim 194303231Sdimconst MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const { 195303231Sdim switch (CC) { 196303231Sdim default: 197303231Sdim llvm_unreachable("Unknown condition code!"); 198303231Sdim case AVRCC::COND_EQ: 199303231Sdim return get(AVR::BREQk); 200303231Sdim case AVRCC::COND_NE: 201303231Sdim return get(AVR::BRNEk); 202303231Sdim case AVRCC::COND_GE: 203303231Sdim return get(AVR::BRGEk); 204303231Sdim case AVRCC::COND_LT: 205303231Sdim return get(AVR::BRLTk); 206303231Sdim case AVRCC::COND_SH: 207303231Sdim return get(AVR::BRSHk); 208303231Sdim case AVRCC::COND_LO: 209303231Sdim return get(AVR::BRLOk); 210303231Sdim case AVRCC::COND_MI: 211303231Sdim return get(AVR::BRMIk); 212303231Sdim case AVRCC::COND_PL: 213303231Sdim return get(AVR::BRPLk); 214303231Sdim } 215303231Sdim} 216303231Sdim 217303231SdimAVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const { 218303231Sdim switch (Opc) { 219303231Sdim default: 220303231Sdim return AVRCC::COND_INVALID; 221303231Sdim case AVR::BREQk: 222303231Sdim return AVRCC::COND_EQ; 223303231Sdim case AVR::BRNEk: 224303231Sdim return AVRCC::COND_NE; 225303231Sdim case AVR::BRSHk: 226303231Sdim return AVRCC::COND_SH; 227303231Sdim case AVR::BRLOk: 228303231Sdim return AVRCC::COND_LO; 229303231Sdim case AVR::BRMIk: 230303231Sdim return AVRCC::COND_MI; 231303231Sdim case AVR::BRPLk: 232303231Sdim return AVRCC::COND_PL; 233303231Sdim case AVR::BRGEk: 234303231Sdim return AVRCC::COND_GE; 235303231Sdim case AVR::BRLTk: 236303231Sdim return AVRCC::COND_LT; 237303231Sdim } 238303231Sdim} 239303231Sdim 240303231SdimAVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const { 241303231Sdim switch (CC) { 242303231Sdim default: 243303231Sdim llvm_unreachable("Invalid condition!"); 244303231Sdim case AVRCC::COND_EQ: 245303231Sdim return AVRCC::COND_NE; 246303231Sdim case AVRCC::COND_NE: 247303231Sdim return AVRCC::COND_EQ; 248303231Sdim case AVRCC::COND_SH: 249303231Sdim return AVRCC::COND_LO; 250303231Sdim case AVRCC::COND_LO: 251303231Sdim return AVRCC::COND_SH; 252303231Sdim case AVRCC::COND_GE: 253303231Sdim return AVRCC::COND_LT; 254303231Sdim case AVRCC::COND_LT: 255303231Sdim return AVRCC::COND_GE; 256303231Sdim case AVRCC::COND_MI: 257303231Sdim return AVRCC::COND_PL; 258303231Sdim case AVRCC::COND_PL: 259303231Sdim return AVRCC::COND_MI; 260303231Sdim } 261303231Sdim} 262303231Sdim 263303231Sdimbool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB, 264303231Sdim MachineBasicBlock *&TBB, 265303231Sdim MachineBasicBlock *&FBB, 266303231Sdim SmallVectorImpl<MachineOperand> &Cond, 267303231Sdim bool AllowModify) const { 268303231Sdim // Start from the bottom of the block and work up, examining the 269303231Sdim // terminator instructions. 270303231Sdim MachineBasicBlock::iterator I = MBB.end(); 271303231Sdim MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 272303231Sdim 273303231Sdim while (I != MBB.begin()) { 274303231Sdim --I; 275341825Sdim if (I->isDebugInstr()) { 276303231Sdim continue; 277303231Sdim } 278303231Sdim 279303231Sdim // Working from the bottom, when we see a non-terminator 280303231Sdim // instruction, we're done. 281303231Sdim if (!isUnpredicatedTerminator(*I)) { 282303231Sdim break; 283303231Sdim } 284303231Sdim 285303231Sdim // A terminator that isn't a branch can't easily be handled 286303231Sdim // by this analysis. 287303231Sdim if (!I->getDesc().isBranch()) { 288303231Sdim return true; 289303231Sdim } 290303231Sdim 291303231Sdim // Handle unconditional branches. 292303231Sdim //:TODO: add here jmp 293303231Sdim if (I->getOpcode() == AVR::RJMPk) { 294303231Sdim UnCondBrIter = I; 295303231Sdim 296303231Sdim if (!AllowModify) { 297303231Sdim TBB = I->getOperand(0).getMBB(); 298303231Sdim continue; 299303231Sdim } 300303231Sdim 301303231Sdim // If the block has any instructions after a JMP, delete them. 302303231Sdim while (std::next(I) != MBB.end()) { 303303231Sdim std::next(I)->eraseFromParent(); 304303231Sdim } 305303231Sdim 306303231Sdim Cond.clear(); 307303231Sdim FBB = 0; 308303231Sdim 309303231Sdim // Delete the JMP if it's equivalent to a fall-through. 310303231Sdim if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 311303231Sdim TBB = 0; 312303231Sdim I->eraseFromParent(); 313303231Sdim I = MBB.end(); 314303231Sdim UnCondBrIter = MBB.end(); 315303231Sdim continue; 316303231Sdim } 317303231Sdim 318303231Sdim // TBB is used to indicate the unconditinal destination. 319303231Sdim TBB = I->getOperand(0).getMBB(); 320303231Sdim continue; 321303231Sdim } 322303231Sdim 323303231Sdim // Handle conditional branches. 324303231Sdim AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); 325303231Sdim if (BranchCode == AVRCC::COND_INVALID) { 326303231Sdim return true; // Can't handle indirect branch. 327303231Sdim } 328303231Sdim 329303231Sdim // Working from the bottom, handle the first conditional branch. 330303231Sdim if (Cond.empty()) { 331303231Sdim MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 332303231Sdim if (AllowModify && UnCondBrIter != MBB.end() && 333303231Sdim MBB.isLayoutSuccessor(TargetBB)) { 334303231Sdim // If we can modify the code and it ends in something like: 335303231Sdim // 336303231Sdim // jCC L1 337303231Sdim // jmp L2 338303231Sdim // L1: 339303231Sdim // ... 340303231Sdim // L2: 341303231Sdim // 342303231Sdim // Then we can change this to: 343303231Sdim // 344303231Sdim // jnCC L2 345303231Sdim // L1: 346303231Sdim // ... 347303231Sdim // L2: 348303231Sdim // 349303231Sdim // Which is a bit more efficient. 350303231Sdim // We conditionally jump to the fall-through block. 351303231Sdim BranchCode = getOppositeCondition(BranchCode); 352303231Sdim unsigned JNCC = getBrCond(BranchCode).getOpcode(); 353303231Sdim MachineBasicBlock::iterator OldInst = I; 354303231Sdim 355303231Sdim BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 356303231Sdim .addMBB(UnCondBrIter->getOperand(0).getMBB()); 357303231Sdim BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(AVR::RJMPk)) 358303231Sdim .addMBB(TargetBB); 359303231Sdim 360303231Sdim OldInst->eraseFromParent(); 361303231Sdim UnCondBrIter->eraseFromParent(); 362303231Sdim 363303231Sdim // Restart the analysis. 364303231Sdim UnCondBrIter = MBB.end(); 365303231Sdim I = MBB.end(); 366303231Sdim continue; 367303231Sdim } 368303231Sdim 369303231Sdim FBB = TBB; 370303231Sdim TBB = I->getOperand(0).getMBB(); 371303231Sdim Cond.push_back(MachineOperand::CreateImm(BranchCode)); 372303231Sdim continue; 373303231Sdim } 374303231Sdim 375303231Sdim // Handle subsequent conditional branches. Only handle the case where all 376303231Sdim // conditional branches branch to the same destination. 377303231Sdim assert(Cond.size() == 1); 378303231Sdim assert(TBB); 379303231Sdim 380303231Sdim // Only handle the case where all conditional branches branch to 381303231Sdim // the same destination. 382303231Sdim if (TBB != I->getOperand(0).getMBB()) { 383303231Sdim return true; 384303231Sdim } 385303231Sdim 386303231Sdim AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); 387303231Sdim // If the conditions are the same, we can leave them alone. 388303231Sdim if (OldBranchCode == BranchCode) { 389303231Sdim continue; 390303231Sdim } 391303231Sdim 392303231Sdim return true; 393303231Sdim } 394303231Sdim 395303231Sdim return false; 396303231Sdim} 397303231Sdim 398314564Sdimunsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB, 399303231Sdim MachineBasicBlock *TBB, 400303231Sdim MachineBasicBlock *FBB, 401303231Sdim ArrayRef<MachineOperand> Cond, 402314564Sdim const DebugLoc &DL, 403314564Sdim int *BytesAdded) const { 404321369Sdim if (BytesAdded) *BytesAdded = 0; 405314564Sdim 406303231Sdim // Shouldn't be a fall through. 407314564Sdim assert(TBB && "insertBranch must not be told to insert a fallthrough"); 408303231Sdim assert((Cond.size() == 1 || Cond.size() == 0) && 409303231Sdim "AVR branch conditions have one component!"); 410303231Sdim 411303231Sdim if (Cond.empty()) { 412303231Sdim assert(!FBB && "Unconditional branch with multiple successors!"); 413321369Sdim auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB); 414321369Sdim if (BytesAdded) 415321369Sdim *BytesAdded += getInstSizeInBytes(MI); 416303231Sdim return 1; 417303231Sdim } 418303231Sdim 419303231Sdim // Conditional branch. 420303231Sdim unsigned Count = 0; 421303231Sdim AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); 422321369Sdim auto &CondMI = *BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB); 423321369Sdim 424321369Sdim if (BytesAdded) *BytesAdded += getInstSizeInBytes(CondMI); 425303231Sdim ++Count; 426303231Sdim 427303231Sdim if (FBB) { 428303231Sdim // Two-way Conditional branch. Insert the second branch. 429321369Sdim auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB); 430321369Sdim if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI); 431303231Sdim ++Count; 432303231Sdim } 433303231Sdim 434303231Sdim return Count; 435303231Sdim} 436303231Sdim 437314564Sdimunsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB, 438314564Sdim int *BytesRemoved) const { 439321369Sdim if (BytesRemoved) *BytesRemoved = 0; 440314564Sdim 441303231Sdim MachineBasicBlock::iterator I = MBB.end(); 442303231Sdim unsigned Count = 0; 443303231Sdim 444303231Sdim while (I != MBB.begin()) { 445303231Sdim --I; 446341825Sdim if (I->isDebugInstr()) { 447303231Sdim continue; 448303231Sdim } 449303231Sdim //:TODO: add here the missing jmp instructions once they are implemented 450303231Sdim // like jmp, {e}ijmp, and other cond branches, ... 451303231Sdim if (I->getOpcode() != AVR::RJMPk && 452303231Sdim getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) { 453303231Sdim break; 454303231Sdim } 455303231Sdim 456303231Sdim // Remove the branch. 457321369Sdim if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I); 458303231Sdim I->eraseFromParent(); 459303231Sdim I = MBB.end(); 460303231Sdim ++Count; 461303231Sdim } 462303231Sdim 463303231Sdim return Count; 464303231Sdim} 465303231Sdim 466314564Sdimbool AVRInstrInfo::reverseBranchCondition( 467303231Sdim SmallVectorImpl<MachineOperand> &Cond) const { 468303231Sdim assert(Cond.size() == 1 && "Invalid AVR branch condition!"); 469303231Sdim 470303231Sdim AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm()); 471303231Sdim Cond[0].setImm(getOppositeCondition(CC)); 472303231Sdim 473303231Sdim return false; 474303231Sdim} 475303231Sdim 476314564Sdimunsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { 477314564Sdim unsigned Opcode = MI.getOpcode(); 478303231Sdim 479303231Sdim switch (Opcode) { 480303231Sdim // A regular instruction 481303231Sdim default: { 482303231Sdim const MCInstrDesc &Desc = get(Opcode); 483303231Sdim return Desc.getSize(); 484303231Sdim } 485303231Sdim case TargetOpcode::EH_LABEL: 486303231Sdim case TargetOpcode::IMPLICIT_DEF: 487303231Sdim case TargetOpcode::KILL: 488303231Sdim case TargetOpcode::DBG_VALUE: 489303231Sdim return 0; 490353358Sdim case TargetOpcode::INLINEASM: 491353358Sdim case TargetOpcode::INLINEASM_BR: { 492314564Sdim const MachineFunction &MF = *MI.getParent()->getParent(); 493314564Sdim const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF.getTarget()); 494314564Sdim const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>(); 495314564Sdim const TargetInstrInfo &TII = *STI.getInstrInfo(); 496314564Sdim 497314564Sdim return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(), 498303231Sdim *TM.getMCAsmInfo()); 499303231Sdim } 500303231Sdim } 501303231Sdim} 502303231Sdim 503321369SdimMachineBasicBlock * 504321369SdimAVRInstrInfo::getBranchDestBlock(const MachineInstr &MI) const { 505321369Sdim switch (MI.getOpcode()) { 506321369Sdim default: 507321369Sdim llvm_unreachable("unexpected opcode!"); 508321369Sdim case AVR::JMPk: 509321369Sdim case AVR::CALLk: 510321369Sdim case AVR::RCALLk: 511321369Sdim case AVR::RJMPk: 512321369Sdim case AVR::BREQk: 513321369Sdim case AVR::BRNEk: 514321369Sdim case AVR::BRSHk: 515321369Sdim case AVR::BRLOk: 516321369Sdim case AVR::BRMIk: 517321369Sdim case AVR::BRPLk: 518321369Sdim case AVR::BRGEk: 519321369Sdim case AVR::BRLTk: 520321369Sdim return MI.getOperand(0).getMBB(); 521321369Sdim case AVR::BRBSsk: 522321369Sdim case AVR::BRBCsk: 523321369Sdim return MI.getOperand(1).getMBB(); 524321369Sdim case AVR::SBRCRrB: 525321369Sdim case AVR::SBRSRrB: 526321369Sdim case AVR::SBICAb: 527321369Sdim case AVR::SBISAb: 528321369Sdim llvm_unreachable("unimplemented branch instructions"); 529321369Sdim } 530321369Sdim} 531321369Sdim 532321369Sdimbool AVRInstrInfo::isBranchOffsetInRange(unsigned BranchOp, 533321369Sdim int64_t BrOffset) const { 534321369Sdim 535321369Sdim switch (BranchOp) { 536321369Sdim default: 537321369Sdim llvm_unreachable("unexpected opcode!"); 538321369Sdim case AVR::JMPk: 539321369Sdim case AVR::CALLk: 540326496Sdim return true; 541321369Sdim case AVR::RCALLk: 542321369Sdim case AVR::RJMPk: 543321369Sdim return isIntN(13, BrOffset); 544321369Sdim case AVR::BRBSsk: 545321369Sdim case AVR::BRBCsk: 546321369Sdim case AVR::BREQk: 547321369Sdim case AVR::BRNEk: 548321369Sdim case AVR::BRSHk: 549321369Sdim case AVR::BRLOk: 550321369Sdim case AVR::BRMIk: 551321369Sdim case AVR::BRPLk: 552321369Sdim case AVR::BRGEk: 553321369Sdim case AVR::BRLTk: 554321369Sdim return isIntN(7, BrOffset); 555321369Sdim } 556321369Sdim} 557321369Sdim 558326496Sdimunsigned AVRInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, 559326496Sdim MachineBasicBlock &NewDestBB, 560326496Sdim const DebugLoc &DL, 561326496Sdim int64_t BrOffset, 562326496Sdim RegScavenger *RS) const { 563326496Sdim // This method inserts a *direct* branch (JMP), despite its name. 564326496Sdim // LLVM calls this method to fixup unconditional branches; it never calls 565326496Sdim // insertBranch or some hypothetical "insertDirectBranch". 566326496Sdim // See lib/CodeGen/RegisterRelaxation.cpp for details. 567326496Sdim // We end up here when a jump is too long for a RJMP instruction. 568326496Sdim auto &MI = *BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB); 569326496Sdim 570326496Sdim return getInstSizeInBytes(MI); 571326496Sdim} 572326496Sdim 573303231Sdim} // end of namespace llvm 574314564Sdim 575