1//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// R600 implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "R600RegisterInfo.h"
15#include "AMDGPUTargetMachine.h"
16#include "R600Defines.h"
17#include "R600InstrInfo.h"
18#include "R600MachineFunctionInfo.h"
19#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20
21using namespace llvm;
22
23R600RegisterInfo::R600RegisterInfo() : R600GenRegisterInfo(0) {
24  RCW.RegWeight = 0;
25  RCW.WeightLimit = 0;
26}
27
28#define GET_REGINFO_TARGET_DESC
29#include "R600GenRegisterInfo.inc"
30
31BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
32  BitVector Reserved(getNumRegs());
33
34  const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
35  const R600InstrInfo *TII = ST.getInstrInfo();
36
37  reserveRegisterTuples(Reserved, R600::ZERO);
38  reserveRegisterTuples(Reserved, R600::HALF);
39  reserveRegisterTuples(Reserved, R600::ONE);
40  reserveRegisterTuples(Reserved, R600::ONE_INT);
41  reserveRegisterTuples(Reserved, R600::NEG_HALF);
42  reserveRegisterTuples(Reserved, R600::NEG_ONE);
43  reserveRegisterTuples(Reserved, R600::PV_X);
44  reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
45  reserveRegisterTuples(Reserved, R600::ALU_CONST);
46  reserveRegisterTuples(Reserved, R600::PREDICATE_BIT);
47  reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF);
48  reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO);
49  reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
50  reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
51
52  for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
53                        E = R600::R600_AddrRegClass.end(); I != E; ++I) {
54    reserveRegisterTuples(Reserved, *I);
55  }
56
57  TII->reserveIndirectRegisters(Reserved, MF, *this);
58
59  return Reserved;
60}
61
62// Dummy to not crash RegisterClassInfo.
63static const MCPhysReg CalleeSavedReg = R600::NoRegister;
64
65const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
66  const MachineFunction *) const {
67  return &CalleeSavedReg;
68}
69
70Register R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
71  return R600::NoRegister;
72}
73
74unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
75  return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
76}
77
78unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
79  return GET_REG_INDEX(getEncodingValue(Reg));
80}
81
82const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
83                                                                   MVT VT) const {
84  switch(VT.SimpleTy) {
85  default:
86  case MVT::i32: return &R600::R600_TReg32RegClass;
87  }
88}
89
90const RegClassWeight &R600RegisterInfo::getRegClassWeight(
91  const TargetRegisterClass *RC) const {
92  return RCW;
93}
94
95bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
96  assert(!Register::isVirtualRegister(Reg));
97
98  switch (Reg) {
99  case R600::OQAP:
100  case R600::OQBP:
101  case R600::AR_X:
102    return false;
103  default:
104    return true;
105  }
106}
107
108void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
109                                           int SPAdj,
110                                           unsigned FIOperandNum,
111                                           RegScavenger *RS) const {
112  llvm_unreachable("Subroutines not supported yet");
113}
114
115void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
116  MCRegAliasIterator R(Reg, this, true);
117
118  for (; R.isValid(); ++R)
119    Reserved.set(*R);
120}
121