/linux-master/drivers/dma/ |
H A D | owl-dma.c | 184 * struct owl_dma_pchan - Holder for the physical channels 219 * @nr_pchans: the number of physical channels 220 * @pchans: array of data for the physical channels 221 * @nr_vchans: the number of physical channels 222 * @vchans: array of data for the physical channels 1056 next, &od->dma.channels, vc.chan.device_node) { 1105 ret = of_property_read_u32(np, "dma-channels", &nr_channels); 1107 dev_err(&pdev->dev, "can't get dma-channels\n"); 1117 dev_info(&pdev->dev, "dma-channels %d, dma-requests %d\n", 1150 INIT_LIST_HEAD(&od->dma.channels); [all...] |
H A D | pch_dma.c | 121 struct pch_dma_chan channels[MAX_CHAN_NR]; member in struct:pch_dma 708 pd_chan = &pd->channels[i]; 749 list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) { 772 list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) { 869 INIT_LIST_HEAD(&pd->dma.channels); 872 struct pch_dma_chan *pd_chan = &pd->channels[i]; 886 list_add_tail(&pd_chan->chan.device_node, &pd->dma.channels); 934 list_for_each_entry_safe(chan, _c, &pd->dma.channels,
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H A D | pl330.c | 449 /* For D-to-M and M-to-D channels */ 469 /* Pool of descriptors available for the DMAC's channels */ 489 struct pl330_thread *channels; member in struct:pl330_dmac 500 /* Peripheral channels connected to this DMAC */ 1599 /* Reset all channels */ 1608 struct pl330_thread *thrd = &pl330->channels[i]; 1667 _stop(&pl330->channels[i]); 1698 thrd = &pl330->channels[id]; 1775 thrd = &pl330->channels[i]; 1890 pl330->channels [all...] |
H A D | plx_dma.c | 520 INIT_LIST_HEAD(&dma->channels); 535 list_add_tail(&chan->device_node, &dma->channels);
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H A D | pxa_dma.c | 354 chandir = debugfs_create_dir("channels", pdev->dbgfs_root); 1218 list_for_each_entry_safe(c, cn, &dmadev->channels, 1310 INIT_LIST_HEAD(&pdev->slave.channels); 1364 /* Parse new and deprecated dma-channels properties */ 1365 if (of_property_read_u32(op->dev.of_node, "dma-channels", 1367 of_property_read_u32(op->dev.of_node, "#dma-channels", 1428 dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n",
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H A D | sa11x0-dma.c | 335 list_for_each_entry(c, &d->slave.channels, vc.chan.device_node) { 498 * channels and trigger the tasklet to run. 532 /* SA11x0 channels can only operate in their native direction */ 612 /* SA11x0 channels can only operate in their native direction */ 840 INIT_LIST_HEAD(&dmadev->channels); 894 list_for_each_entry_safe(c, cn, &dmadev->channels, vc.chan.device_node) {
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H A D | sprd-dma.c | 215 struct sprd_dma_chn channels[] __counted_by(total_chns); 233 return container_of(schan, struct sprd_dma_dev, channels[c->chan_id]); 601 schan = &sdev->channels[i]; 1127 /* Parse new and deprecated dma-channels properties */ 1128 ret = device_property_read_u32(&pdev->dev, "dma-channels", &chn_count); 1130 ret = device_property_read_u32(&pdev->dev, "#dma-channels", 1133 dev_err(&pdev->dev, "get dma channels count failed\n"); 1138 struct_size(sdev, channels, chn_count), 1179 INIT_LIST_HEAD(&sdev->dma_dev.channels); 1194 dma_chn = &sdev->channels[ [all...] |
H A D | st_fdma.c | 41 * dreq_mask is shared for n channels of fdma, so all accesses must be 720 return of_property_read_u32(pdev->dev.of_node, "dma-channels", 786 /* Initialise list of FDMA channels */ 787 INIT_LIST_HEAD(&fdev->dma_device.channels);
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H A D | ste_dma40.c | 34 * @disabled_channels: A vector, ending with -1, that marks physical channels 36 * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW 40 * @num_of_soft_lli_chans: The number of channels that needs to be configured 43 * @num_of_memcpy_chans: The number of channels reserved for memcpy. 44 * @num_of_phy_chans: The number of physical channels implemented in HW. 45 * 0 means reading the number of channels from DMA HW but this is only valid 46 * for 'multiple of 4' channels, like 8. 78 /* Max number of logical channels per physical channel */ 315 /* Interrupts on all logical channels */ 333 /* Interrupts on all logical channels */ [all...] |
H A D | stm32-dma.c | 1550 dev_err(dev, "No more channels available\n"); 1637 INIT_LIST_HEAD(&dd->channels);
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H A D | stm32-mdma.c | 1574 dev_err(mdma2dev(dmadev), "No more channels available\n"); 1604 ret = device_property_read_u32(&pdev->dev, "dma-channels", 1608 dev_warn(&pdev->dev, "MDMA defaulting on %i channels\n", 1695 INIT_LIST_HEAD(&dd->channels);
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H A D | sun4i-dma.c | 104 * Normal DMA has 8 channels, and Dedicated DMA has another 8, so 105 * that's 16 channels. As for endpoints, there's 29 and 21 1178 INIT_LIST_HEAD(&priv->slave.channels);
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H A D | sun6i-dma.c | 42 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */ 116 * Hardware channels / ports representation 119 * of channels and endpoints. This structure ties those numbers 485 list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) { 516 /* Remove from pending channels */ 1082 * There's 16 physical channels that can work in parallel. 1086 * Since the channels are able to handle only an unidirectional 1087 * transfer, we need to allocate more virtual channels so that 1091 * wouldn't make sense), so we have a bit fewer virtual channels than 1092 * 2 channels pe [all...] |
H A D | tegra186-gpc-dma.c | 174 * @nr_channels: Number of channels available in the controller. 257 struct tegra_dma_channel channels[]; member in struct:tegra_dma 442 * This is useful to recover channels that can exit out of flush 1362 struct_size(tdma, channels, cdata->nr_channels), 1398 INIT_LIST_HEAD(&tdma->dma_dev.channels); 1400 struct tegra_dma_channel *tdc = &tdma->channels[i]; 1471 dev_info(&pdev->dev, "GPC DMA driver register %lu channels\n", 1491 struct tegra_dma_channel *tdc = &tdma->channels[i]; 1513 struct tegra_dma_channel *tdc = &tdma->channels[i];
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/linux-master/drivers/dma/ppc4xx/ |
H A D | adma.c | 71 /* The list of channels exported by ppc440spe ADMA */ 4123 INIT_LIST_HEAD(&adev->common.channels); 4140 list_add_tail(&chan->common.device_node, &adev->common.channels); 4247 list_for_each_entry_safe(chan, _chan, &adev->common.channels,
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/linux-master/drivers/dma/ptdma/ |
H A D | ptdma-dmaengine.c | 369 INIT_LIST_HEAD(&dma_dev->channels);
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/linux-master/drivers/dma/qcom/ |
H A D | bam_dma.c | 9 * peripherals on the MSM 8x74. The configuration of the channels are dependent 384 struct bam_chan *channels; member in struct:bam_device 839 struct bam_chan *bchan = &bdev->channels[i]; 1122 /* go through the channels and kick off transactions */ 1124 bchan = &bdev->channels[i]; 1181 return dma_get_slave_channel(&(bdev->channels[request].vc.chan)); 1284 ret = of_property_read_u32(pdev->dev.of_node, "num-channels", 1287 dev_err(bdev->dev, "num-channels unspecified in dt\n"); 1307 bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels, 1308 sizeof(*bdev->channels), GFP_KERNE [all...] |
H A D | gpi.c | 362 * @ACTIVE_STATE: channels are fully operational 363 * @PREPARE_TERMINATE: graceful termination of channels 365 * @PAUSE_STATE: channels are active, but not processing any events 1484 * treat both channels as a group if its protocol is not UART 1503 /* reset the channels (clears any pending tre) */ 1521 /* restart the channels */ 1537 /* pause dma transfer for all channels */ 1556 /* send stop command to stop the channels */ 1594 /* send start command to start the channels */ 1899 /* check if both channels ar [all...] |
H A D | hidma.c | 95 INIT_LIST_HEAD(&dmadev->ddev.channels); 216 list_add_tail(&mchan->chan.device_node, &ddev->channels); 796 INIT_LIST_HEAD(&dmadev->ddev.channels); 872 INIT_LIST_HEAD(&dmadev->ddev.channels);
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H A D | qcom_adm.c | 162 struct adm_chan *channels; member in struct:adm_device 580 struct adm_chan *achan = &adev->channels[i]; 728 list_for_each_entry(chan, &dev->channels, device_node) 828 adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS, 829 sizeof(*adev->channels), GFP_KERNEL); 831 if (!adev->channels) { 836 /* allocate and initialize channels */ 837 INIT_LIST_HEAD(&adev->common.channels); 840 adm_channel_init(adev, &adev->channels[i], i); 917 achan = &adev->channels[ [all...] |
/linux-master/drivers/dma/sf-pdma/ |
H A D | sf-pdma.c | 391 * Initialize DONE and ERROR interrupt handler for 4 channels. Caller should 456 INIT_LIST_HEAD(&pdma->dma_dev.channels); 507 ret = of_property_read_u32(pdev->dev.of_node, "dma-channels", &n_chans); 509 /* backwards-compatibility for no dma-channels property */ 510 dev_dbg(&pdev->dev, "set number of channels to default value: 4\n"); 513 dev_err(&pdev->dev, "the number of channels exceeds the maximum\n");
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/linux-master/drivers/dma/sh/ |
H A D | rcar-dmac.c | 194 * @n_channels: number of available channels 195 * @channels: array of DMAC channels 196 * @channels_mask: bitfield of which DMA channels are managed by this driver 206 struct rcar_dmac_chan *channels; member in struct:rcar_dmac 215 for (i = 0, chan = &(dmac)->channels[0]; i < (dmac)->n_channels; i++, chan++) \ 220 * @chan_offset_base: DMAC channels base offset 221 * @chan_offset_stride: DMAC channels offset stride 480 /* Clear all channels and enable the DMAC globally. */ 854 /* Stop all channels [all...] |
H A D | rz-dmac.c | 100 struct rz_dmac_chan *channels; member in struct:rz_dmac 744 /* Only slave DMA channels can be allocated via DT */ 828 ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels); 830 dev_err(dev, "unable to read dma-channels property\n"); 835 dev_err(dev, "invalid number of channels %u\n", dmac->n_channels); 863 dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels, 864 sizeof(*dmac->channels), GFP_KERNEL); 865 if (!dmac->channels) 890 /* Initialize the channels. */ 891 INIT_LIST_HEAD(&dmac->engine.channels); [all...] |
H A D | shdma-base.c | 41 * system, and that each such slave can only use a finite number of channels. 281 /* Only support channels handled by this driver. */ 851 /* Reset all channels */ 970 &sdev->dma_dev.channels); 1007 INIT_LIST_HEAD(&dma_dev->channels);
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H A D | usb-dmac.c | 94 * @n_channels: number of available channels 95 * @channels: array of DMAC channels 103 struct usb_dmac_chan *channels; member in struct:usb_dmac 248 /* Clear all channels and enable the DMAC globally. */ 349 /* Don't issue soft reset if any one of channels is busy */ 657 /* Only slave DMA channels can be allocated via DT */ 680 if (!dmac->channels[i].iomem) 682 usb_dmac_chan_halt(&dmac->channels[i]); 751 ret = of_property_read_u32(np, "dma-channels", [all...] |