Searched refs:mmio (Results 101 - 125 of 429) sorted by relevance

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/linux-master/drivers/spi/
H A Dspi-ep93xx.c71 * @mmio: pointer to ioremap()'d registers
88 void __iomem *mmio; member in struct:ep93xx_spi
173 writel(div_cpsr, espi->mmio + SSPCPSR);
174 writel(cr0, espi->mmio + SSPCR0);
194 writel(val, espi->mmio + SSPDR);
203 val = readl(espi->mmio + SSPDR);
232 while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) {
447 if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) {
449 writel(0, espi->mmio + SSPICR);
473 val = readl(espi->mmio
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/linux-master/drivers/comedi/drivers/
H A Dmite.c208 unsigned int fcr_bits = readl(mite->mmio + MITE_FCR(channel));
219 return readl(mite->mmio + MITE_DAR(mite_chan->channel));
230 return readl(mite->mmio + MITE_FCR(mite_chan->channel)) & 0xff;
367 status = readl(mite->mmio + MITE_CHSR(mite_chan->channel));
371 mite->mmio + MITE_CHOR(mite_chan->channel));
394 writel(CHOR_CLRLC, mite->mmio + MITE_CHOR(mite_chan->channel));
431 mite_chan->mite->mmio + MITE_CHOR(mite_chan->channel));
451 writel(CHOR_START, mite->mmio + MITE_CHOR(mite_chan->channel));
465 writel(CHOR_ABORT, mite->mmio + MITE_CHOR(mite_chan->channel));
508 writel(chcr, mite->mmio
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H A Dgsc_hpdi.c42 * PCI BAR2 Register map (dev->mmio)
196 hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
197 hpdi_board_status = readl(dev->mmio + BOARD_STATUS_REG);
200 writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG);
266 writel(0, dev->mmio + BOARD_CONTROL_REG);
267 writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
286 writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
319 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG);
322 writel(RX_FULL_INTR, dev->mmio + INTERRUPT_CONTROL_REG);
324 writel(RX_ENABLE_BIT, dev->mmio
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H A Daddi_apci_3xxx.c355 status = readl(dev->mmio + 16);
358 writel(status, dev->mmio + 16);
360 val = readl(dev->mmio + 28);
373 if ((readl(dev->mmio + 8) & 0x80000) == 0x80000)
391 writel(0x10000, dev->mmio + 12);
394 delay_mode = readl(dev->mmio + 4);
398 writel(delay_mode, dev->mmio + 4);
403 writel(val, dev->mmio + 0);
406 writel(delay_mode | 0x100, dev->mmio + 4);
407 writel(chan, dev->mmio
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/linux-master/drivers/ssb/
H A Dhost_soc.c21 return readb(bus->mmio + offset);
29 return readw(bus->mmio + offset);
37 return readl(bus->mmio + offset);
48 addr = bus->mmio + offset;
94 writeb(value, bus->mmio + offset);
102 writew(value, bus->mmio + offset);
110 writel(value, bus->mmio + offset);
121 addr = bus->mmio + offset;
/linux-master/drivers/watchdog/
H A Dvia_wdt.c69 static unsigned int mmio; variable
186 pci_read_config_dword(pdev, VIA_WDT_MMIO_BASE, &mmio);
187 if (mmio) {
188 dev_info(&pdev->dev, "VIA Chipset watchdog MMIO: %x\n", mmio);
194 if (!request_mem_region(mmio, VIA_WDT_MMIO_LEN, "via_wdt")) {
199 wdt_mem = ioremap(mmio, VIA_WDT_MMIO_LEN);
225 release_mem_region(mmio, VIA_WDT_MMIO_LEN);
238 release_mem_region(mmio, VIA_WDT_MMIO_LEN);
/linux-master/drivers/mfd/
H A Drz-mtu3.c23 void __iomem *mmio; member in struct:rz_mtu3_priv
71 return readw(priv->mmio + offset);
73 return readb(priv->mmio + offset);
85 return readb(priv->mmio + ch_offs);
101 return readw(priv->mmio + ch_offs);
116 return readl(priv->mmio + ch_offs);
127 writeb(val, priv->mmio + ch_offs);
142 writew(val, priv->mmio + ch_offs);
156 writel(val, priv->mmio + ch_offs);
166 writew(value, priv->mmio
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/linux-master/drivers/gpu/drm/xe/
H A Dxe_mmio.c329 regs = xe->mmio.regs;
331 tile->mmio.size = tile_mmio_size;
332 tile->mmio.regs = regs;
343 regs = xe->mmio.regs + tile_mmio_size * tile_count;
358 pci_iounmap(to_pci_dev(xe->drm.dev), xe->mmio.regs);
397 xe->mmio.size = pci_resource_len(pdev, mmio_bar);
398 xe->mmio.regs = pci_iomap(pdev, mmio_bar, 0);
399 if (xe->mmio.regs == NULL) {
413 root_tile->mmio.size = SZ_16M;
414 root_tile->mmio
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/linux-master/sound/soc/sof/mediatek/mt8186/
H A Dmt8186.c92 struct resource *mmio; local
134 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
135 if (!mmio) {
140 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
144 adsp->pa_cfgreg = (phys_addr_t)mmio->start;
145 adsp->cfgregsize = resource_size(mmio);
149 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
150 if (!mmio) {
155 adsp->pa_sram = (phys_addr_t)mmio->start;
156 adsp->sramsize = resource_size(mmio);
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/linux-master/drivers/ata/
H A Dsata_mv.c577 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
579 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
581 void __iomem *mmio);
582 int (*reset_hc)(struct ata_host *host, void __iomem *mmio,
584 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
585 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
604 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
606 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
608 void __iomem *mmio);
609 static int mv5_reset_hc(struct ata_host *host, void __iomem *mmio,
881 mv5_phy_base(void __iomem *mmio, unsigned int port) argument
1064 void __iomem *mmio = hpriv->base, *hc_mmio; local
2852 void __iomem *mmio = hpriv->base, *hc_mmio; local
2914 mv_pci_error(struct ata_host *host, void __iomem *mmio) argument
3024 void __iomem *mmio = hpriv->base; local
3038 void __iomem *mmio = hpriv->base; local
3049 mv5_reset_bus(struct ata_host *host, void __iomem *mmio) argument
3065 mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3070 mv5_read_preamp(struct mv_host_priv *hpriv, int idx, void __iomem *mmio) argument
3082 mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3095 mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3124 mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3148 mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int hc) argument
3166 mv5_reset_hc(struct ata_host *host, void __iomem *mmio, unsigned int n_hc) argument
3185 mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) argument
3207 mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3228 mv6_reset_hc(struct ata_host *host, void __iomem *mmio, unsigned int n_hc) argument
3283 mv6_read_preamp(struct mv_host_priv *hpriv, int idx, void __iomem *mmio) argument
3303 mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3308 mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3386 mv_soc_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3392 mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, void __iomem *mmio) argument
3407 mv_soc_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3432 mv_soc_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3445 mv_soc_reset_hc(struct ata_host *host, void __iomem *mmio, unsigned int n_hc) argument
3459 mv_soc_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) argument
3465 mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) argument
3470 mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3527 mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port_no) argument
3593 void __iomem *mmio = hpriv->base; local
3695 void __iomem *mmio = hpriv->base; local
3709 void __iomem *mmio = hpriv->base; local
3723 void __iomem *mmio = hpriv->base; local
3890 void __iomem *mmio = hpriv->base; local
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H A Dsata_svw.c129 void __iomem *mmio = link->ap->ioaddr.bmdma_addr; local
131 dmactl = readb(mmio + ATA_DMA_CMD);
136 writeb(dmactl, mmio + ATA_DMA_CMD);
146 void __iomem *mmio = link->ap->ioaddr.bmdma_addr; local
148 dmactl = readb(mmio + ATA_DMA_CMD);
153 writeb(dmactl, mmio + ATA_DMA_CMD);
236 void __iomem *mmio = ap->ioaddr.bmdma_addr; local
240 writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
243 dmactl = readb(mmio + ATA_DMA_CMD);
247 writeb(dmactl, mmio
265 void __iomem *mmio = ap->ioaddr.bmdma_addr; local
[all...]
H A Dahci_st.c38 static void st_ahci_configure_oob(void __iomem *mmio) argument
47 old_val = readl(mmio + ST_AHCI_OOBR);
48 writel(old_val | ST_AHCI_OOBR_WE, mmio + ST_AHCI_OOBR);
49 writel(new_val | ST_AHCI_OOBR_WE, mmio + ST_AHCI_OOBR);
50 writel(new_val, mmio + ST_AHCI_OOBR);
167 st_ahci_configure_oob(hpriv->mmio);
220 st_ahci_configure_oob(hpriv->mmio);
/linux-master/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.h148 void __iomem *mmio; member in struct:etnaviv_gpu
168 writel(data, gpu->mmio + reg);
173 return readl(gpu->mmio + reg);
188 writel(data, gpu->mmio + gpu_fix_power_address(gpu, reg));
193 return readl(gpu->mmio + gpu_fix_power_address(gpu, reg));
/linux-master/drivers/gpu/drm/loongson/
H A Dlsdc_pixpll.c106 iounmap(this->mmio);
122 this->mmio = ioremap(this->reg_base, this->reg_size);
123 if (!this->mmio)
128 iounmap(this->mmio);
255 dst->d = readq(this->mmio);
257 dst->w[0] = readl(this->mmio);
258 dst->w[1] = readl(this->mmio + 4);
266 writeq(src->d, this->mmio);
268 writel(src->w[0], this->mmio);
269 writel(src->w[1], this->mmio
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/linux-master/drivers/input/keyboard/
H A Dtegra-kbc.c90 void __iomem *mmio; member in struct:tegra_kbc
156 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
233 val = readl(kbc->mmio + KBC_CONTROL_0);
238 writel(val, kbc->mmio + KBC_CONTROL_0);
250 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
289 val = readl(kbc->mmio + KBC_INT_0);
290 writel(val, kbc->mmio + KBC_INT_0);
318 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
332 u32 row_cfg = readl(kbc->mmio + r_offs);
333 u32 col_cfg = readl(kbc->mmio
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/linux-master/drivers/gpu/drm/tiny/
H A Dbochs.c75 void __iomem *mmio; member in struct:bochs_device
103 if (bochs->mmio) {
106 writeb(val, bochs->mmio + offset);
117 if (bochs->mmio) {
120 return readb(bochs->mmio + offset);
130 if (bochs->mmio) {
133 ret = readw(bochs->mmio + offset);
143 if (bochs->mmio) {
146 writew(val, bochs->mmio + offset);
158 writel(0xbebebebe, bochs->mmio
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H A Dcirrus.c68 void __iomem *mmio; member in struct:cirrus_device
102 iowrite8(reg, cirrus->mmio + SEQ_INDEX);
103 return ioread8(cirrus->mmio + SEQ_DATA);
108 iowrite8(reg, cirrus->mmio + SEQ_INDEX);
109 iowrite8(val, cirrus->mmio + SEQ_DATA);
117 iowrite8(reg, cirrus->mmio + CRT_INDEX);
118 return ioread8(cirrus->mmio + CRT_DATA);
123 iowrite8(reg, cirrus->mmio + CRT_INDEX);
124 iowrite8(val, cirrus->mmio + CRT_DATA);
132 iowrite8(reg, cirrus->mmio
[all...]
/linux-master/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dmmio.c216 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len);
221 memcpy_fromio(buf, dev->mt76.mmio.regs +
274 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed);
290 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) {
306 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
318 wed = &dev->mt76.mmio.wed_hif2;
486 spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
488 mdev->mmio.irqmask &= ~clear;
489 mdev->mmio.irqmask |= set;
492 if (mtk_wed_device_active(&mdev->mmio
[all...]
/linux-master/drivers/bcma/
H A Dhost_soc.c175 bus->mmio = ioremap(BCMA_ADDR_BASE, BCMA_CORE_SIZE * 1);
176 if (!bus->mmio)
197 iounmap(bus->mmio);
218 bus->mmio = of_iomap(np, 0);
219 if (!bus->mmio)
239 iounmap(bus->mmio);
248 iounmap(bus->mmio);
/linux-master/drivers/video/fbdev/
H A Dpmag-aa-fb.c65 void __iomem *mmio; member in struct:aafb_par
188 par->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
189 if (!par->mmio) {
194 par->bt455 = par->mmio - PMAG_AA_BT455_OFFSET + PMAG_AA_BT455_OFFSET;
195 par->bt431 = par->mmio - PMAG_AA_BT455_OFFSET + PMAG_AA_BT431_OFFSET;
235 iounmap(par->mmio);
255 iounmap(par->mmio);
/linux-master/drivers/powercap/
H A Dintel_rapl_tpmi.c63 if (!ra->reg.mmio)
66 ra->value = readq(ra->reg.mmio);
76 if (!ra->reg.mmio)
79 val = readq(ra->reg.mmio);
84 writeq(val, ra->reg.mmio);
197 if (trp->priv.regs[domain_type][RAPL_DOMAIN_REG_UNIT].mmio) {
235 trp->priv.regs[domain_type][reg_id].mmio = trp->base + offset + reg_index * 8;
/linux-master/sound/soc/sof/intel/
H A Dbyt.c115 struct resource *mmio; local
135 mmio = platform_get_resource(pdev, IORESOURCE_MEM,
137 if (mmio) {
138 base = mmio->start;
139 size = resource_size(mmio);
163 mmio = platform_get_resource(pdev, IORESOURCE_MEM,
165 if (mmio) {
166 base = mmio->start;
167 size = resource_size(mmio);
226 /* Register IO uses direct mmio */
[all...]
/linux-master/arch/m68k/virt/
H A Dints.c39 * IRQ #1 to IRQ #32 -> virtio-mmio from 1 to 32
41 * IRQ #1 to IRQ #32 -> virtio-mmio from 33 to 64
43 * IRQ #1 to IRQ #32 -> virtio-mmio from 65 to 96
45 * IRQ #1 to IRQ #32 -> virtio-mmio from 97 to 128
55 void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio +
63 void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio +
140 DEFINE_RES_MEM_NAMED(virt_bi_data.pic.mmio + i * 0x1000,
/linux-master/drivers/media/platform/renesas/vsp1/
H A Dvsp1.h82 void __iomem *mmio; member in struct:vsp1_device
119 return ioread32(vsp1->mmio + reg);
124 iowrite32(data, vsp1->mmio + reg);
/linux-master/drivers/i2c/busses/
H A Di2c-amd-mp2-pci.c50 reg = privdata->mmio + ((i2c_cmd_base.s.bus_id == 1) ?
97 memcpy_toio(privdata->mmio + AMD_C2P_MSG2,
103 privdata->mmio + AMD_C2P_MSG2);
154 privdata->mmio + AMD_C2P_MSG2,
216 reg = privdata->mmio + ((bus_id == 0) ?
221 writel(0, privdata->mmio + AMD_P2C_MSG_INTEN);
230 val = readl(privdata->mmio + AMD_P2C_MSG_INTEN);
232 writel(0, privdata->mmio + AMD_P2C_MSG_INTEN);
282 writel(0, privdata->mmio + reg);
285 writel(0, privdata->mmio
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