1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * comedi/drivers/mite.c 4 * Hardware driver for NI Mite PCI interface chip 5 * 6 * COMEDI - Linux Control and Measurement Device Interface 7 * Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org> 8 */ 9 10/* 11 * The PCI-MIO E series driver was originally written by 12 * Tomasz Motylewski <...>, and ported to comedi by ds. 13 * 14 * References for specifications: 15 * 16 * 321747b.pdf Register Level Programmer Manual (obsolete) 17 * 321747c.pdf Register Level Programmer Manual (new) 18 * DAQ-STC reference manual 19 * 20 * Other possibly relevant info: 21 * 22 * 320517c.pdf User manual (obsolete) 23 * 320517f.pdf User manual (new) 24 * 320889a.pdf delete 25 * 320906c.pdf maximum signal ratings 26 * 321066a.pdf about 16x 27 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c 28 * 321808a.pdf about at-mio-16e-10 rev P 29 * 321837a.pdf discontinuation of at-mio-16de-10 rev d 30 * 321838a.pdf about at-mio-16de-10 rev N 31 * 32 * ISSUES: 33 * 34 */ 35 36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 37 38#include <linux/module.h> 39#include <linux/slab.h> 40#include <linux/log2.h> 41#include <linux/comedi/comedi_pci.h> 42 43#include "mite.h" 44 45/* 46 * Mite registers 47 */ 48#define MITE_UNKNOWN_DMA_BURST_REG 0x28 49#define UNKNOWN_DMA_BURST_ENABLE_BITS 0x600 50 51#define MITE_PCI_CONFIG_OFFSET 0x300 52#define MITE_CSIGR 0x460 /* chip signature */ 53#define CSIGR_TO_IOWINS(x) (((x) >> 29) & 0x7) 54#define CSIGR_TO_WINS(x) (((x) >> 24) & 0x1f) 55#define CSIGR_TO_WPDEP(x) (((x) >> 20) & 0x7) 56#define CSIGR_TO_DMAC(x) (((x) >> 16) & 0xf) 57#define CSIGR_TO_IMODE(x) (((x) >> 12) & 0x3) /* pci=0x3 */ 58#define CSIGR_TO_MMODE(x) (((x) >> 8) & 0x3) /* minimite=1 */ 59#define CSIGR_TO_TYPE(x) (((x) >> 4) & 0xf) /* mite=0, minimite=1 */ 60#define CSIGR_TO_VER(x) (((x) >> 0) & 0xf) 61 62#define MITE_CHAN(x) (0x500 + 0x100 * (x)) 63#define MITE_CHOR(x) (0x00 + MITE_CHAN(x)) /* channel operation */ 64#define CHOR_DMARESET BIT(31) 65#define CHOR_SET_SEND_TC BIT(11) 66#define CHOR_CLR_SEND_TC BIT(10) 67#define CHOR_SET_LPAUSE BIT(9) 68#define CHOR_CLR_LPAUSE BIT(8) 69#define CHOR_CLRDONE BIT(7) 70#define CHOR_CLRRB BIT(6) 71#define CHOR_CLRLC BIT(5) 72#define CHOR_FRESET BIT(4) 73#define CHOR_ABORT BIT(3) /* stop without emptying fifo */ 74#define CHOR_STOP BIT(2) /* stop after emptying fifo */ 75#define CHOR_CONT BIT(1) 76#define CHOR_START BIT(0) 77#define MITE_CHCR(x) (0x04 + MITE_CHAN(x)) /* channel control */ 78#define CHCR_SET_DMA_IE BIT(31) 79#define CHCR_CLR_DMA_IE BIT(30) 80#define CHCR_SET_LINKP_IE BIT(29) 81#define CHCR_CLR_LINKP_IE BIT(28) 82#define CHCR_SET_SAR_IE BIT(27) 83#define CHCR_CLR_SAR_IE BIT(26) 84#define CHCR_SET_DONE_IE BIT(25) 85#define CHCR_CLR_DONE_IE BIT(24) 86#define CHCR_SET_MRDY_IE BIT(23) 87#define CHCR_CLR_MRDY_IE BIT(22) 88#define CHCR_SET_DRDY_IE BIT(21) 89#define CHCR_CLR_DRDY_IE BIT(20) 90#define CHCR_SET_LC_IE BIT(19) 91#define CHCR_CLR_LC_IE BIT(18) 92#define CHCR_SET_CONT_RB_IE BIT(17) 93#define CHCR_CLR_CONT_RB_IE BIT(16) 94#define CHCR_FIFO(x) (((x) & 0x1) << 15) 95#define CHCR_FIFODIS CHCR_FIFO(1) 96#define CHCR_FIFO_ON CHCR_FIFO(0) 97#define CHCR_BURST(x) (((x) & 0x1) << 14) 98#define CHCR_BURSTEN CHCR_BURST(1) 99#define CHCR_NO_BURSTEN CHCR_BURST(0) 100#define CHCR_BYTE_SWAP_DEVICE BIT(6) 101#define CHCR_BYTE_SWAP_MEMORY BIT(4) 102#define CHCR_DIR(x) (((x) & 0x1) << 3) 103#define CHCR_DEV_TO_MEM CHCR_DIR(1) 104#define CHCR_MEM_TO_DEV CHCR_DIR(0) 105#define CHCR_MODE(x) (((x) & 0x7) << 0) 106#define CHCR_NORMAL CHCR_MODE(0) 107#define CHCR_CONTINUE CHCR_MODE(1) 108#define CHCR_RINGBUFF CHCR_MODE(2) 109#define CHCR_LINKSHORT CHCR_MODE(4) 110#define CHCR_LINKLONG CHCR_MODE(5) 111#define MITE_TCR(x) (0x08 + MITE_CHAN(x)) /* transfer count */ 112#define MITE_MCR(x) (0x0c + MITE_CHAN(x)) /* memory config */ 113#define MITE_MAR(x) (0x10 + MITE_CHAN(x)) /* memory address */ 114#define MITE_DCR(x) (0x14 + MITE_CHAN(x)) /* device config */ 115#define DCR_NORMAL BIT(29) 116#define MITE_DAR(x) (0x18 + MITE_CHAN(x)) /* device address */ 117#define MITE_LKCR(x) (0x1c + MITE_CHAN(x)) /* link config */ 118#define MITE_LKAR(x) (0x20 + MITE_CHAN(x)) /* link address */ 119#define MITE_LLKAR(x) (0x24 + MITE_CHAN(x)) /* see tnt5002 manual */ 120#define MITE_BAR(x) (0x28 + MITE_CHAN(x)) /* base address */ 121#define MITE_BCR(x) (0x2c + MITE_CHAN(x)) /* base count */ 122#define MITE_SAR(x) (0x30 + MITE_CHAN(x)) /* ? address */ 123#define MITE_WSCR(x) (0x34 + MITE_CHAN(x)) /* ? */ 124#define MITE_WSER(x) (0x38 + MITE_CHAN(x)) /* ? */ 125#define MITE_CHSR(x) (0x3c + MITE_CHAN(x)) /* channel status */ 126#define CHSR_INT BIT(31) 127#define CHSR_LPAUSES BIT(29) 128#define CHSR_SARS BIT(27) 129#define CHSR_DONE BIT(25) 130#define CHSR_MRDY BIT(23) 131#define CHSR_DRDY BIT(21) 132#define CHSR_LINKC BIT(19) 133#define CHSR_CONTS_RB BIT(17) 134#define CHSR_ERROR BIT(15) 135#define CHSR_SABORT BIT(14) 136#define CHSR_HABORT BIT(13) 137#define CHSR_STOPS BIT(12) 138#define CHSR_OPERR(x) (((x) & 0x3) << 10) 139#define CHSR_OPERR_MASK CHSR_OPERR(3) 140#define CHSR_OPERR_NOERROR CHSR_OPERR(0) 141#define CHSR_OPERR_FIFOERROR CHSR_OPERR(1) 142#define CHSR_OPERR_LINKERROR CHSR_OPERR(1) /* ??? */ 143#define CHSR_XFERR BIT(9) 144#define CHSR_END BIT(8) 145#define CHSR_DRQ1 BIT(7) 146#define CHSR_DRQ0 BIT(6) 147#define CHSR_LERR(x) (((x) & 0x3) << 4) 148#define CHSR_LERR_MASK CHSR_LERR(3) 149#define CHSR_LBERR CHSR_LERR(1) 150#define CHSR_LRERR CHSR_LERR(2) 151#define CHSR_LOERR CHSR_LERR(3) 152#define CHSR_MERR(x) (((x) & 0x3) << 2) 153#define CHSR_MERR_MASK CHSR_MERR(3) 154#define CHSR_MBERR CHSR_MERR(1) 155#define CHSR_MRERR CHSR_MERR(2) 156#define CHSR_MOERR CHSR_MERR(3) 157#define CHSR_DERR(x) (((x) & 0x3) << 0) 158#define CHSR_DERR_MASK CHSR_DERR(3) 159#define CHSR_DBERR CHSR_DERR(1) 160#define CHSR_DRERR CHSR_DERR(2) 161#define CHSR_DOERR CHSR_DERR(3) 162#define MITE_FCR(x) (0x40 + MITE_CHAN(x)) /* fifo count */ 163 164/* common bits for the memory/device/link config registers */ 165#define CR_RL(x) (((x) & 0x7) << 21) 166#define CR_REQS(x) (((x) & 0x7) << 16) 167#define CR_REQS_MASK CR_REQS(7) 168#define CR_ASEQ(x) (((x) & 0x3) << 10) 169#define CR_ASEQDONT CR_ASEQ(0) 170#define CR_ASEQUP CR_ASEQ(1) 171#define CR_ASEQDOWN CR_ASEQ(2) 172#define CR_ASEQ_MASK CR_ASEQ(3) 173#define CR_PSIZE(x) (((x) & 0x3) << 8) 174#define CR_PSIZE8 CR_PSIZE(1) 175#define CR_PSIZE16 CR_PSIZE(2) 176#define CR_PSIZE32 CR_PSIZE(3) 177#define CR_PORT(x) (((x) & 0x3) << 6) 178#define CR_PORTCPU CR_PORT(0) 179#define CR_PORTIO CR_PORT(1) 180#define CR_PORTVXI CR_PORT(2) 181#define CR_PORTMXI CR_PORT(3) 182#define CR_AMDEVICE BIT(0) 183 184static unsigned int MITE_IODWBSR_1_WSIZE_bits(unsigned int size) 185{ 186 return (ilog2(size) - 1) & 0x1f; 187} 188 189static unsigned int mite_retry_limit(unsigned int retry_limit) 190{ 191 unsigned int value = 0; 192 193 if (retry_limit) 194 value = 1 + ilog2(retry_limit); 195 if (value > 0x7) 196 value = 0x7; 197 return CR_RL(value); 198} 199 200static unsigned int mite_drq_reqs(unsigned int drq_line) 201{ 202 /* This also works on m-series when using channels (drq_line) 4 or 5. */ 203 return CR_REQS((drq_line & 0x3) | 0x4); 204} 205 206static unsigned int mite_fifo_size(struct mite *mite, unsigned int channel) 207{ 208 unsigned int fcr_bits = readl(mite->mmio + MITE_FCR(channel)); 209 unsigned int empty_count = (fcr_bits >> 16) & 0xff; 210 unsigned int full_count = fcr_bits & 0xff; 211 212 return empty_count + full_count; 213} 214 215static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan) 216{ 217 struct mite *mite = mite_chan->mite; 218 219 return readl(mite->mmio + MITE_DAR(mite_chan->channel)); 220} 221 222/** 223 * mite_bytes_in_transit() - Returns the number of unread bytes in the fifo. 224 * @mite_chan: MITE dma channel. 225 */ 226u32 mite_bytes_in_transit(struct mite_channel *mite_chan) 227{ 228 struct mite *mite = mite_chan->mite; 229 230 return readl(mite->mmio + MITE_FCR(mite_chan->channel)) & 0xff; 231} 232EXPORT_SYMBOL_GPL(mite_bytes_in_transit); 233 234/* returns lower bound for number of bytes transferred from device to memory */ 235static u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan) 236{ 237 u32 device_byte_count; 238 239 device_byte_count = mite_device_bytes_transferred(mite_chan); 240 return device_byte_count - mite_bytes_in_transit(mite_chan); 241} 242 243/* returns upper bound for number of bytes transferred from device to memory */ 244static u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan) 245{ 246 u32 in_transit_count; 247 248 in_transit_count = mite_bytes_in_transit(mite_chan); 249 return mite_device_bytes_transferred(mite_chan) - in_transit_count; 250} 251 252/* returns lower bound for number of bytes read from memory to device */ 253static u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan) 254{ 255 u32 device_byte_count; 256 257 device_byte_count = mite_device_bytes_transferred(mite_chan); 258 return device_byte_count + mite_bytes_in_transit(mite_chan); 259} 260 261/* returns upper bound for number of bytes read from memory to device */ 262static u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan) 263{ 264 u32 in_transit_count; 265 266 in_transit_count = mite_bytes_in_transit(mite_chan); 267 return mite_device_bytes_transferred(mite_chan) + in_transit_count; 268} 269 270static void mite_sync_input_dma(struct mite_channel *mite_chan, 271 struct comedi_subdevice *s) 272{ 273 struct comedi_async *async = s->async; 274 int count; 275 unsigned int nbytes, old_alloc_count; 276 277 old_alloc_count = async->buf_write_alloc_count; 278 /* write alloc as much as we can */ 279 comedi_buf_write_alloc(s, async->prealloc_bufsz); 280 281 nbytes = mite_bytes_written_to_memory_lb(mite_chan); 282 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) - 283 old_alloc_count) > 0) { 284 dev_warn(s->device->class_dev, 285 "mite: DMA overwrite of free area\n"); 286 async->events |= COMEDI_CB_OVERFLOW; 287 return; 288 } 289 290 count = nbytes - async->buf_write_count; 291 /* 292 * it's possible count will be negative due to conservative value 293 * returned by mite_bytes_written_to_memory_lb 294 */ 295 if (count > 0) { 296 comedi_buf_write_free(s, count); 297 comedi_inc_scan_progress(s, count); 298 async->events |= COMEDI_CB_BLOCK; 299 } 300} 301 302static void mite_sync_output_dma(struct mite_channel *mite_chan, 303 struct comedi_subdevice *s) 304{ 305 struct comedi_async *async = s->async; 306 struct comedi_cmd *cmd = &async->cmd; 307 u32 stop_count = cmd->stop_arg * comedi_bytes_per_scan(s); 308 unsigned int old_alloc_count = async->buf_read_alloc_count; 309 u32 nbytes_ub, nbytes_lb; 310 int count; 311 bool finite_regen = (cmd->stop_src == TRIG_NONE && stop_count != 0); 312 313 /* read alloc as much as we can */ 314 comedi_buf_read_alloc(s, async->prealloc_bufsz); 315 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan); 316 if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_lb - stop_count) > 0) 317 nbytes_lb = stop_count; 318 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan); 319 if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_ub - stop_count) > 0) 320 nbytes_ub = stop_count; 321 322 if ((!finite_regen || stop_count > old_alloc_count) && 323 ((int)(nbytes_ub - old_alloc_count) > 0)) { 324 dev_warn(s->device->class_dev, "mite: DMA underrun\n"); 325 async->events |= COMEDI_CB_OVERFLOW; 326 return; 327 } 328 329 if (finite_regen) { 330 /* 331 * This is a special case where we continuously output a finite 332 * buffer. In this case, we do not free any of the memory, 333 * hence we expect that old_alloc_count will reach a maximum of 334 * stop_count bytes. 335 */ 336 return; 337 } 338 339 count = nbytes_lb - async->buf_read_count; 340 if (count > 0) { 341 comedi_buf_read_free(s, count); 342 async->events |= COMEDI_CB_BLOCK; 343 } 344} 345 346/** 347 * mite_sync_dma() - Sync the MITE dma with the COMEDI async buffer. 348 * @mite_chan: MITE dma channel. 349 * @s: COMEDI subdevice. 350 */ 351void mite_sync_dma(struct mite_channel *mite_chan, struct comedi_subdevice *s) 352{ 353 if (mite_chan->dir == COMEDI_INPUT) 354 mite_sync_input_dma(mite_chan, s); 355 else 356 mite_sync_output_dma(mite_chan, s); 357} 358EXPORT_SYMBOL_GPL(mite_sync_dma); 359 360static unsigned int mite_get_status(struct mite_channel *mite_chan) 361{ 362 struct mite *mite = mite_chan->mite; 363 unsigned int status; 364 unsigned long flags; 365 366 spin_lock_irqsave(&mite->lock, flags); 367 status = readl(mite->mmio + MITE_CHSR(mite_chan->channel)); 368 if (status & CHSR_DONE) { 369 mite_chan->done = 1; 370 writel(CHOR_CLRDONE, 371 mite->mmio + MITE_CHOR(mite_chan->channel)); 372 } 373 spin_unlock_irqrestore(&mite->lock, flags); 374 return status; 375} 376 377/** 378 * mite_ack_linkc() - Check and ack the LINKC interrupt, 379 * @mite_chan: MITE dma channel. 380 * @s: COMEDI subdevice. 381 * @sync: flag to force a mite_sync_dma(). 382 * 383 * This will also ack the DONE interrupt if active. 384 */ 385void mite_ack_linkc(struct mite_channel *mite_chan, 386 struct comedi_subdevice *s, 387 bool sync) 388{ 389 struct mite *mite = mite_chan->mite; 390 unsigned int status; 391 392 status = mite_get_status(mite_chan); 393 if (status & CHSR_LINKC) { 394 writel(CHOR_CLRLC, mite->mmio + MITE_CHOR(mite_chan->channel)); 395 sync = true; 396 } 397 if (sync) 398 mite_sync_dma(mite_chan, s); 399 400 if (status & CHSR_XFERR) { 401 dev_err(s->device->class_dev, 402 "mite: transfer error %08x\n", status); 403 s->async->events |= COMEDI_CB_ERROR; 404 } 405} 406EXPORT_SYMBOL_GPL(mite_ack_linkc); 407 408/** 409 * mite_done() - Check is a MITE dma transfer is complete. 410 * @mite_chan: MITE dma channel. 411 * 412 * This will also ack the DONE interrupt if active. 413 */ 414int mite_done(struct mite_channel *mite_chan) 415{ 416 struct mite *mite = mite_chan->mite; 417 unsigned long flags; 418 int done; 419 420 mite_get_status(mite_chan); 421 spin_lock_irqsave(&mite->lock, flags); 422 done = mite_chan->done; 423 spin_unlock_irqrestore(&mite->lock, flags); 424 return done; 425} 426EXPORT_SYMBOL_GPL(mite_done); 427 428static void mite_dma_reset(struct mite_channel *mite_chan) 429{ 430 writel(CHOR_DMARESET | CHOR_FRESET, 431 mite_chan->mite->mmio + MITE_CHOR(mite_chan->channel)); 432} 433 434/** 435 * mite_dma_arm() - Start a MITE dma transfer. 436 * @mite_chan: MITE dma channel. 437 */ 438void mite_dma_arm(struct mite_channel *mite_chan) 439{ 440 struct mite *mite = mite_chan->mite; 441 unsigned long flags; 442 443 /* 444 * memory barrier is intended to insure any twiddling with the buffer 445 * is done before writing to the mite to arm dma transfer 446 */ 447 smp_mb(); 448 spin_lock_irqsave(&mite->lock, flags); 449 mite_chan->done = 0; 450 /* arm */ 451 writel(CHOR_START, mite->mmio + MITE_CHOR(mite_chan->channel)); 452 spin_unlock_irqrestore(&mite->lock, flags); 453} 454EXPORT_SYMBOL_GPL(mite_dma_arm); 455 456/** 457 * mite_dma_disarm() - Stop a MITE dma transfer. 458 * @mite_chan: MITE dma channel. 459 */ 460void mite_dma_disarm(struct mite_channel *mite_chan) 461{ 462 struct mite *mite = mite_chan->mite; 463 464 /* disarm */ 465 writel(CHOR_ABORT, mite->mmio + MITE_CHOR(mite_chan->channel)); 466} 467EXPORT_SYMBOL_GPL(mite_dma_disarm); 468 469/** 470 * mite_prep_dma() - Prepare a MITE dma channel for transfers. 471 * @mite_chan: MITE dma channel. 472 * @num_device_bits: device transfer size (8, 16, or 32-bits). 473 * @num_memory_bits: memory transfer size (8, 16, or 32-bits). 474 */ 475void mite_prep_dma(struct mite_channel *mite_chan, 476 unsigned int num_device_bits, unsigned int num_memory_bits) 477{ 478 struct mite *mite = mite_chan->mite; 479 unsigned int chcr, mcr, dcr, lkcr; 480 481 mite_dma_reset(mite_chan); 482 483 /* short link chaining mode */ 484 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE | 485 CHCR_BURSTEN; 486 /* 487 * Link Complete Interrupt: interrupt every time a link 488 * in MITE_RING is completed. This can generate a lot of 489 * extra interrupts, but right now we update the values 490 * of buf_int_ptr and buf_int_count at each interrupt. A 491 * better method is to poll the MITE before each user 492 * "read()" to calculate the number of bytes available. 493 */ 494 chcr |= CHCR_SET_LC_IE; 495 if (num_memory_bits == 32 && num_device_bits == 16) { 496 /* 497 * Doing a combined 32 and 16 bit byteswap gets the 16 bit 498 * samples into the fifo in the right order. Tested doing 32 bit 499 * memory to 16 bit device transfers to the analog out of a 500 * pxi-6281, which has mite version = 1, type = 4. This also 501 * works for dma reads from the counters on e-series boards. 502 */ 503 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY; 504 } 505 if (mite_chan->dir == COMEDI_INPUT) 506 chcr |= CHCR_DEV_TO_MEM; 507 508 writel(chcr, mite->mmio + MITE_CHCR(mite_chan->channel)); 509 510 /* to/from memory */ 511 mcr = mite_retry_limit(64) | CR_ASEQUP; 512 switch (num_memory_bits) { 513 case 8: 514 mcr |= CR_PSIZE8; 515 break; 516 case 16: 517 mcr |= CR_PSIZE16; 518 break; 519 case 32: 520 mcr |= CR_PSIZE32; 521 break; 522 default: 523 pr_warn("bug! invalid mem bit width for dma transfer\n"); 524 break; 525 } 526 writel(mcr, mite->mmio + MITE_MCR(mite_chan->channel)); 527 528 /* from/to device */ 529 dcr = mite_retry_limit(64) | CR_ASEQUP; 530 dcr |= CR_PORTIO | CR_AMDEVICE | mite_drq_reqs(mite_chan->channel); 531 switch (num_device_bits) { 532 case 8: 533 dcr |= CR_PSIZE8; 534 break; 535 case 16: 536 dcr |= CR_PSIZE16; 537 break; 538 case 32: 539 dcr |= CR_PSIZE32; 540 break; 541 default: 542 pr_warn("bug! invalid dev bit width for dma transfer\n"); 543 break; 544 } 545 writel(dcr, mite->mmio + MITE_DCR(mite_chan->channel)); 546 547 /* reset the DAR */ 548 writel(0, mite->mmio + MITE_DAR(mite_chan->channel)); 549 550 /* the link is 32bits */ 551 lkcr = mite_retry_limit(64) | CR_ASEQUP | CR_PSIZE32; 552 writel(lkcr, mite->mmio + MITE_LKCR(mite_chan->channel)); 553 554 /* starting address for link chaining */ 555 writel(mite_chan->ring->dma_addr, 556 mite->mmio + MITE_LKAR(mite_chan->channel)); 557} 558EXPORT_SYMBOL_GPL(mite_prep_dma); 559 560/** 561 * mite_request_channel_in_range() - Request a MITE dma channel. 562 * @mite: MITE device. 563 * @ring: MITE dma ring. 564 * @min_channel: minimum channel index to use. 565 * @max_channel: maximum channel index to use. 566 */ 567struct mite_channel *mite_request_channel_in_range(struct mite *mite, 568 struct mite_ring *ring, 569 unsigned int min_channel, 570 unsigned int max_channel) 571{ 572 struct mite_channel *mite_chan = NULL; 573 unsigned long flags; 574 int i; 575 576 /* 577 * spin lock so mite_release_channel can be called safely 578 * from interrupts 579 */ 580 spin_lock_irqsave(&mite->lock, flags); 581 for (i = min_channel; i <= max_channel; ++i) { 582 mite_chan = &mite->channels[i]; 583 if (!mite_chan->ring) { 584 mite_chan->ring = ring; 585 break; 586 } 587 mite_chan = NULL; 588 } 589 spin_unlock_irqrestore(&mite->lock, flags); 590 return mite_chan; 591} 592EXPORT_SYMBOL_GPL(mite_request_channel_in_range); 593 594/** 595 * mite_request_channel() - Request a MITE dma channel. 596 * @mite: MITE device. 597 * @ring: MITE dma ring. 598 */ 599struct mite_channel *mite_request_channel(struct mite *mite, 600 struct mite_ring *ring) 601{ 602 return mite_request_channel_in_range(mite, ring, 0, 603 mite->num_channels - 1); 604} 605EXPORT_SYMBOL_GPL(mite_request_channel); 606 607/** 608 * mite_release_channel() - Release a MITE dma channel. 609 * @mite_chan: MITE dma channel. 610 */ 611void mite_release_channel(struct mite_channel *mite_chan) 612{ 613 struct mite *mite = mite_chan->mite; 614 unsigned long flags; 615 616 /* spin lock to prevent races with mite_request_channel */ 617 spin_lock_irqsave(&mite->lock, flags); 618 if (mite_chan->ring) { 619 mite_dma_disarm(mite_chan); 620 mite_dma_reset(mite_chan); 621 /* 622 * disable all channel's interrupts (do it after disarm/reset so 623 * MITE_CHCR reg isn't changed while dma is still active!) 624 */ 625 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | 626 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE | 627 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | 628 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, 629 mite->mmio + MITE_CHCR(mite_chan->channel)); 630 mite_chan->ring = NULL; 631 } 632 spin_unlock_irqrestore(&mite->lock, flags); 633} 634EXPORT_SYMBOL_GPL(mite_release_channel); 635 636/** 637 * mite_init_ring_descriptors() - Initialize a MITE dma ring descriptors. 638 * @ring: MITE dma ring. 639 * @s: COMEDI subdevice. 640 * @nbytes: the size of the dma ring (in bytes). 641 * 642 * Initializes the ring buffer descriptors to provide correct DMA transfer 643 * links to the exact amount of memory required. When the ring buffer is 644 * allocated by mite_buf_change(), the default is to initialize the ring 645 * to refer to the entire DMA data buffer. A command may call this function 646 * later to re-initialize and shorten the amount of memory that will be 647 * transferred. 648 */ 649int mite_init_ring_descriptors(struct mite_ring *ring, 650 struct comedi_subdevice *s, 651 unsigned int nbytes) 652{ 653 struct comedi_async *async = s->async; 654 struct mite_dma_desc *desc = NULL; 655 unsigned int n_full_links = nbytes >> PAGE_SHIFT; 656 unsigned int remainder = nbytes % PAGE_SIZE; 657 int i; 658 659 dev_dbg(s->device->class_dev, 660 "mite: init ring buffer to %u bytes\n", nbytes); 661 662 if ((n_full_links + (remainder > 0 ? 1 : 0)) > ring->n_links) { 663 dev_err(s->device->class_dev, 664 "mite: ring buffer too small for requested init\n"); 665 return -ENOMEM; 666 } 667 668 /* We set the descriptors for all full links. */ 669 for (i = 0; i < n_full_links; ++i) { 670 desc = &ring->descs[i]; 671 desc->count = cpu_to_le32(PAGE_SIZE); 672 desc->addr = cpu_to_le32(async->buf_map->page_list[i].dma_addr); 673 desc->next = cpu_to_le32(ring->dma_addr + 674 (i + 1) * sizeof(*desc)); 675 } 676 677 /* the last link is either a remainder or was a full link. */ 678 if (remainder > 0) { 679 desc = &ring->descs[i]; 680 /* set the lesser count for the remainder link */ 681 desc->count = cpu_to_le32(remainder); 682 desc->addr = cpu_to_le32(async->buf_map->page_list[i].dma_addr); 683 } 684 685 /* Assign the last link->next to point back to the head of the list. */ 686 desc->next = cpu_to_le32(ring->dma_addr); 687 688 /* 689 * barrier is meant to insure that all the writes to the dma descriptors 690 * have completed before the dma controller is commanded to read them 691 */ 692 smp_wmb(); 693 return 0; 694} 695EXPORT_SYMBOL_GPL(mite_init_ring_descriptors); 696 697static void mite_free_dma_descs(struct mite_ring *ring) 698{ 699 struct mite_dma_desc *descs = ring->descs; 700 701 if (descs) { 702 dma_free_coherent(ring->hw_dev, 703 ring->n_links * sizeof(*descs), 704 descs, ring->dma_addr); 705 ring->descs = NULL; 706 ring->dma_addr = 0; 707 ring->n_links = 0; 708 } 709} 710 711/** 712 * mite_buf_change() - COMEDI subdevice (*buf_change) for a MITE dma ring. 713 * @ring: MITE dma ring. 714 * @s: COMEDI subdevice. 715 */ 716int mite_buf_change(struct mite_ring *ring, struct comedi_subdevice *s) 717{ 718 struct comedi_async *async = s->async; 719 struct mite_dma_desc *descs; 720 unsigned int n_links; 721 722 mite_free_dma_descs(ring); 723 724 if (async->prealloc_bufsz == 0) 725 return 0; 726 727 n_links = async->prealloc_bufsz >> PAGE_SHIFT; 728 729 descs = dma_alloc_coherent(ring->hw_dev, 730 n_links * sizeof(*descs), 731 &ring->dma_addr, GFP_KERNEL); 732 if (!descs) { 733 dev_err(s->device->class_dev, 734 "mite: ring buffer allocation failed\n"); 735 return -ENOMEM; 736 } 737 ring->descs = descs; 738 ring->n_links = n_links; 739 740 return mite_init_ring_descriptors(ring, s, n_links << PAGE_SHIFT); 741} 742EXPORT_SYMBOL_GPL(mite_buf_change); 743 744/** 745 * mite_alloc_ring() - Allocate a MITE dma ring. 746 * @mite: MITE device. 747 */ 748struct mite_ring *mite_alloc_ring(struct mite *mite) 749{ 750 struct mite_ring *ring; 751 752 ring = kmalloc(sizeof(*ring), GFP_KERNEL); 753 if (!ring) 754 return NULL; 755 ring->hw_dev = get_device(&mite->pcidev->dev); 756 if (!ring->hw_dev) { 757 kfree(ring); 758 return NULL; 759 } 760 ring->n_links = 0; 761 ring->descs = NULL; 762 ring->dma_addr = 0; 763 return ring; 764} 765EXPORT_SYMBOL_GPL(mite_alloc_ring); 766 767/** 768 * mite_free_ring() - Free a MITE dma ring and its descriptors. 769 * @ring: MITE dma ring. 770 */ 771void mite_free_ring(struct mite_ring *ring) 772{ 773 if (ring) { 774 mite_free_dma_descs(ring); 775 put_device(ring->hw_dev); 776 kfree(ring); 777 } 778} 779EXPORT_SYMBOL_GPL(mite_free_ring); 780 781static int mite_setup(struct comedi_device *dev, struct mite *mite, 782 bool use_win1) 783{ 784 resource_size_t daq_phys_addr; 785 unsigned long length; 786 int i; 787 u32 csigr_bits; 788 unsigned int unknown_dma_burst_bits; 789 unsigned int wpdep; 790 791 pci_set_master(mite->pcidev); 792 793 mite->mmio = pci_ioremap_bar(mite->pcidev, 0); 794 if (!mite->mmio) 795 return -ENOMEM; 796 797 dev->mmio = pci_ioremap_bar(mite->pcidev, 1); 798 if (!dev->mmio) 799 return -ENOMEM; 800 daq_phys_addr = pci_resource_start(mite->pcidev, 1); 801 length = pci_resource_len(mite->pcidev, 1); 802 803 if (use_win1) { 804 writel(0, mite->mmio + MITE_IODWBSR); 805 dev_dbg(dev->class_dev, 806 "mite: using I/O Window Base Size register 1\n"); 807 writel(daq_phys_addr | WENAB | 808 MITE_IODWBSR_1_WSIZE_bits(length), 809 mite->mmio + MITE_IODWBSR_1); 810 writel(0, mite->mmio + MITE_IODWCR_1); 811 } else { 812 writel(daq_phys_addr | WENAB, mite->mmio + MITE_IODWBSR); 813 } 814 /* 815 * Make sure dma bursts work. I got this from running a bus analyzer 816 * on a pxi-6281 and a pxi-6713. 6713 powered up with register value 817 * of 0x61f and bursts worked. 6281 powered up with register value of 818 * 0x1f and bursts didn't work. The NI windows driver reads the 819 * register, then does a bitwise-or of 0x600 with it and writes it back. 820 * 821 * The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be 822 * written and read back. The bits 0x1f always read as 1. 823 * The rest always read as zero. 824 */ 825 unknown_dma_burst_bits = readl(mite->mmio + MITE_UNKNOWN_DMA_BURST_REG); 826 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS; 827 writel(unknown_dma_burst_bits, mite->mmio + MITE_UNKNOWN_DMA_BURST_REG); 828 829 csigr_bits = readl(mite->mmio + MITE_CSIGR); 830 mite->num_channels = CSIGR_TO_DMAC(csigr_bits); 831 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) { 832 dev_warn(dev->class_dev, 833 "mite: bug? chip claims to have %i dma channels. Setting to %i.\n", 834 mite->num_channels, MAX_MITE_DMA_CHANNELS); 835 mite->num_channels = MAX_MITE_DMA_CHANNELS; 836 } 837 838 /* get the wpdep bits and convert it to the write port fifo depth */ 839 wpdep = CSIGR_TO_WPDEP(csigr_bits); 840 if (wpdep) 841 wpdep = BIT(wpdep); 842 843 dev_dbg(dev->class_dev, 844 "mite: version = %i, type = %i, mite mode = %i, interface mode = %i\n", 845 CSIGR_TO_VER(csigr_bits), CSIGR_TO_TYPE(csigr_bits), 846 CSIGR_TO_MMODE(csigr_bits), CSIGR_TO_IMODE(csigr_bits)); 847 dev_dbg(dev->class_dev, 848 "mite: num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n", 849 CSIGR_TO_DMAC(csigr_bits), wpdep, 850 CSIGR_TO_WINS(csigr_bits), CSIGR_TO_IOWINS(csigr_bits)); 851 852 for (i = 0; i < mite->num_channels; i++) { 853 writel(CHOR_DMARESET, mite->mmio + MITE_CHOR(i)); 854 /* disable interrupts */ 855 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | 856 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | 857 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE, 858 mite->mmio + MITE_CHCR(i)); 859 } 860 mite->fifo_size = mite_fifo_size(mite, 0); 861 dev_dbg(dev->class_dev, "mite: fifo size is %i.\n", mite->fifo_size); 862 return 0; 863} 864 865/** 866 * mite_attach() - Allocate and initialize a MITE device for a comedi driver. 867 * @dev: COMEDI device. 868 * @use_win1: flag to use I/O Window 1 instead of I/O Window 0. 869 * 870 * Called by a COMEDI drivers (*auto_attach). 871 * 872 * Returns a pointer to the MITE device on success, or NULL if the MITE cannot 873 * be allocated or remapped. 874 */ 875struct mite *mite_attach(struct comedi_device *dev, bool use_win1) 876{ 877 struct pci_dev *pcidev = comedi_to_pci_dev(dev); 878 struct mite *mite; 879 unsigned int i; 880 int ret; 881 882 mite = kzalloc(sizeof(*mite), GFP_KERNEL); 883 if (!mite) 884 return NULL; 885 886 spin_lock_init(&mite->lock); 887 mite->pcidev = pcidev; 888 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) { 889 mite->channels[i].mite = mite; 890 mite->channels[i].channel = i; 891 mite->channels[i].done = 1; 892 } 893 894 ret = mite_setup(dev, mite, use_win1); 895 if (ret) { 896 if (mite->mmio) 897 iounmap(mite->mmio); 898 kfree(mite); 899 return NULL; 900 } 901 902 return mite; 903} 904EXPORT_SYMBOL_GPL(mite_attach); 905 906/** 907 * mite_detach() - Unmap and free a MITE device for a comedi driver. 908 * @mite: MITE device. 909 * 910 * Called by a COMEDI drivers (*detach). 911 */ 912void mite_detach(struct mite *mite) 913{ 914 if (!mite) 915 return; 916 917 if (mite->mmio) 918 iounmap(mite->mmio); 919 920 kfree(mite); 921} 922EXPORT_SYMBOL_GPL(mite_detach); 923 924static int __init mite_module_init(void) 925{ 926 return 0; 927} 928module_init(mite_module_init); 929 930static void __exit mite_module_exit(void) 931{ 932} 933module_exit(mite_module_exit); 934 935MODULE_AUTHOR("Comedi https://www.comedi.org"); 936MODULE_DESCRIPTION("Comedi helper for NI Mite PCI interface chip"); 937MODULE_LICENSE("GPL"); 938